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公开(公告)号：US09813169B2
公开(公告)日：2017-11-07
申请号：US14946360
申请日：2015-11-19
Inventor： Josef Einzinger , Sudipto Chakraborty
Abstract: An RF or other high frequency transceiver including a loopback reference channel for measurement of an absolute power level. A transmit channel in the transceiver includes a programmable power amplifier that can be controlled to operate at a selected power level, and a receive channel including a receive amplifier, mixers, filters, and analog-to-digital converters. The loopback reference channel includes a self-biased amplifier, followed by a series of buffers that generate a square wave from the received signal, and an attenuator applying an attenuation gain to the square wave. The transmit power at a programmed power level can be calculated from ratios of a measured power level of a transmitted signal as received by the receive channel to the measured power level of the transmitted signal using the loopback reference channel.
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公开(公告)号：US09712143B2
公开(公告)日：2017-07-18
申请号：US14971655
申请日：2015-12-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudipto Chakraborty
CPC classification number: H03K5/131 , H03K2005/00058 , H03K2005/00286 , H03M1/745
Abstract: A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals.
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公开(公告)号：US09647669B1
公开(公告)日：2017-05-09
申请号：US15212411
申请日：2016-07-18
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty
CPC classification number: H03K23/44
Abstract: Disclosed examples include frequency divider circuits, comprising an even number 4 or more differential delay circuits coupled in a cascade ring configuration of a configurable length N, with N−K of the N delay circuits providing an inverted polarity output signal to a succeeding delay circuit in the cascade ring configuration to control an amount of overlap between phase shifted clock signals from the delay circuits.
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公开(公告)号：US09438304B2
公开(公告)日：2016-09-06
申请号：US14825714
申请日：2015-08-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： June Chul Roh , Anuj Batra , Sudipto Chakraborty , Srinath Hosur
IPC: H04B1/00 , H04B1/69 , H04B1/7176
CPC classification number: H04B1/69 , H04B1/7176 , H04B2001/6908
Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.
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公开(公告)号：US20150349834A1
公开(公告)日：2015-12-03
申请号：US14821194
申请日：2015-08-07
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty
CPC classification number: H04B1/40 , H04W52/02 , H04W52/0261 , Y02D70/00 , Y02D70/144 , Y02D70/40
Abstract: Integrated circuit transceiver circuitry (2) includes a first resonant circuit (3A) coupled to a narrowband interface (6,7A,7B,21) between a first amplifier (3,20) and an interfacing circuit (4,8,9,44), including a programmable first reactive element (C) and a second reactive element (L). Amplitude sensing circuitry (42) senses a maximum amplitude of an in-phase signal (I) or a quadrature-phase signal (Q). An on-chip first tone generation circuit (38,38A,38B,38C) generates tones for injection into the in-phase signal and the quadrature-phase signal and operates in response to frequency scanning circuitry (30) and the amplitude sensing circuitry to adjust the first reactive element (C) to calibrate the first resonant circuit to a desired resonant frequency by selectively coupling reactive sub-elements (1,2,4,8 . . . ×Cv) into the first reactive element (C).
Abstract translation: 集成电路收发器电路（2）包括耦合到第一放大器（3,20）和接口电路（4,8,9,44）之间的窄带接口（6,7A，7B，21）的第一谐振电路（3A） ），包括可编程的第一电抗元件（C）和第二电抗元件（L）。 幅度感测电路（42）感测同相信号（I）或正交相位信号（Q）的最大振幅。 片上第一音调产生电路（38,38A，38B，38C）产生用于注入到同相信号和正交相位信号中的音调，并响应于频率扫描电路（30）和振幅检测电路 通过选择性地将反应子元件（1,2,4,8 ...×Cv）耦合到第一反应元件（C）中，来调节第一电抗元件（C）以将第一谐振电路校准到期望的谐振频率。
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Patent Agency Ranking
公开(公告)号：US20150280772A1
公开(公告)日：2015-10-01
申请号：US14740961
申请日：2015-06-16
Inventor： Sudipto Chakraborty , David LeDeaut , Josef Einzinger , Jens Graul , Vadim Valerievich Ivanov
CPC classification number: H04B1/401 , H03F3/24 , H04B1/0458 , H04B1/18 , H04B2001/0408
Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.
Abstract translation: 芯片上的系统（SoC）包括收发器，其包括发射器和接收器，其中发射器和接收器中的至少一个具有可配置部分，其可被配置为以单端模式和差分模式操作。 提供两个接口引脚用于通过匹配网络将收发器耦合到天线，其中两个接口引脚可共享地耦合到发射器和接收器。 可调电容器耦合到可配置部分的差分信号线，其中可调谐电容器被配置为调整以优化每个操作模式的可配置部分的阻抗匹配。
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公开(公告)号：US09136899B2
公开(公告)日：2015-09-15
申请号：US13908203
申请日：2013-06-03
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty
CPC classification number: H04B1/40 , H04W52/02 , H04W52/0261 , Y02D70/00 , Y02D70/144 , Y02D70/40
Abstract: Integrated circuit transceiver circuitry (2) includes a first resonant circuit (3A) coupled to a narrowband interface (6,7A,7B,21) between a first amplifier (3,20) and an interfacing circuit (4,8,9,44), including a programmable first reactive element (C) and a second reactive element (L). Amplitude sensing circuitry (42) senses a maximum amplitude of an in-phase signal (I) or a quadrature-phase signal (Q). An on-chip first tone generation circuit (38,38A,38B,38C) generates tones for injection into the in-phase signal and the quadrature-phase signal and operates in response to frequency scanning circuitry (30) and the amplitude sensing circuitry to adjust the first reactive element (C) to calibrate the first resonant circuit to a desired resonant frequency by selectively coupling reactive sub-elements (1,2,4,8 . . . ×Cv) into the first reactive element (C).
Abstract translation: 集成电路收发器电路（2）包括耦合到第一放大器（3,20）和接口电路（4,8,9,44）之间的窄带接口（6,7A，7B，21）的第一谐振电路（3A） ），包括可编程的第一电抗元件（C）和第二电抗元件（L）。 幅度感测电路（42）感测同相信号（I）或正交相位信号（Q）的最大振幅。 片上第一音调产生电路（38,38A，38B，38C）产生用于注入到同相信号和正交相位信号中的音调，并响应于频率扫描电路（30）和振幅检测电路 通过选择性地将反应子元件（1,2,4,8 ...×Cv）耦合到第一反应元件（C）中，来调节第一电抗元件（C）以将第一谐振电路校准到期望的谐振频率。
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公开(公告)号：US09088334B2
公开(公告)日：2015-07-21
申请号：US13748008
申请日：2013-01-23
Inventor： Sudipto Chakraborty , David LeDeaut , Josef Einzinger , Jens Graul , Vadim Valerievich Ivanov
CPC classification number: H04B1/401 , H03F3/24 , H04B1/0458 , H04B1/18 , H04B2001/0408
Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.
Abstract translation: 芯片上的系统（SoC）包括收发器，其包括发射器和接收器，其中发射器和接收器中的至少一个具有可配置部分，其可被配置为以单端模式和差分模式操作。 提供两个接口引脚用于通过匹配网络将收发器耦合到天线，其中两个接口引脚可共享地耦合到发射器和接收器。 可调电容器耦合到可配置部分的差分信号线，其中可调谐电容器被配置为调整以优化每个操作模式的可配置部分的阻抗匹配。
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公开(公告)号：US20140355655A1
公开(公告)日：2014-12-04
申请号：US13908203
申请日：2013-06-03
Applicant: Texas Instruments Incorporated
Inventor： Sudipto Chakraborty
CPC classification number: H04B1/40 , H04W52/02 , H04W52/0261 , Y02D70/00 , Y02D70/144 , Y02D70/40
Abstract: Integrated circuit transceiver circuitry (2) includes a first resonant circuit (3A) coupled to a narrowband interface (6,7A,7B,21) between a first amplifier (3,20) and an interfacing circuit (4,8,9,44), including a programmable first reactive element (C) and a second reactive element (L). Amplitude sensing circuitry (42) senses a maximum amplitude of an in-phase signal (I) or a quadrature-phase signal (Q). An on-chip first tone generation circuit (38,38A,38B,38C) generates tones for injection into the in-phase signal and the quadrature-phase signal and operates in response to frequency scanning circuitry (30) and the amplitude sensing circuitry to adjust the first reactive element (C) to calibrate the first resonant circuit to a desired resonant frequency by selectively coupling reactive sub-elements (1,2,4,8 . . . ×Cv) into the first reactive element (C).
Abstract translation: 集成电路收发器电路（2）包括耦合到第一放大器（3,20）和接口电路（4,8,9,44）之间的窄带接口（6,7A，7B，21）的第一谐振电路（3A） ），包括可编程的第一电抗元件（C）和第二电抗元件（L）。 幅度感测电路（42）感测同相信号（I）或正交相位信号（Q）的最大振幅。 片上第一音调产生电路（38,38A，38B，38C）产生用于注入到同相信号和正交相位信号中的音调，并响应于频率扫描电路（30）和振幅检测电路 通过选择性地将反应子元件（1,2,4,8 ...×Cv）耦合到第一反应元件（C）中，来调节第一电抗元件（C）以将第一谐振电路校准到期望的谐振频率。
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公开(公告)号：US20140206296A1
公开(公告)日：2014-07-24
申请号：US13748008
申请日：2013-01-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudipto Chakraborty , David LeDeaut , Josef Einzinger , Jens Graul , Vadim Valerievich Ivanov
IPC: H04B1/40
CPC classification number: H04B1/401 , H03F3/24 , H04B1/0458 , H04B1/18 , H04B2001/0408
Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.
Abstract translation: 芯片上的系统（SoC）包括收发器，其包括发射器和接收器，其中发射器和接收器中的至少一个具有可配置部分，其可被配置为以单端模式和差分模式操作。 提供两个接口引脚用于通过匹配网络将收发器耦合到天线，其中两个接口引脚可共享地耦合到发射器和接收器。 可调电容器耦合到可配置部分的差分信号线，其中可调谐电容器被配置为调整以优化每个操作模式的可配置部分的阻抗匹配。
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