公开(公告)号：US20240379752A1

公开(公告)日：2024-11-14

申请号：US18783081

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.

公开(公告)号：US20240282840A1

公开(公告)日：2024-08-22

申请号：US18653928

申请日：2024-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Yi CHUANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785

Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

公开(公告)号：US20230253453A1

公开(公告)日：2023-08-10

申请号：US18295248

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Jia-Ni YU ,  Chung-Wei HSU ,  Chih-Hao WANG ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Mao-Lin HUANG

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0669 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/785 ,  H01L29/66795

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

公开(公告)号：US20230238429A1

公开(公告)日：2023-07-27

申请号：US18295246

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Jia-Ni YU ,  Chung-Wei HSU ,  Chih-Hao WANG ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Mao-Lin HUANG

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0669 ,  H01L27/0924 ,  H01L21/823431 ,  H01L29/785 ,  H01L29/66795

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

公开(公告)号：US20230122250A1

公开(公告)日：2023-04-20

申请号：US17737915

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Chih-Hao Wang ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234

Abstract: A device includes a substrate, first and second gate structures, first and second hybrid fins, and first and second sidewalls. The first gate structure is over and surrounds a first vertical stack of nanostructures. The second gate structure is over and surrounds a second vertical stack of nanostructures. The second gate structure and the first gate structure extend along a first direction, and are laterally separated from each other in a second direction, the second direction being substantially perpendicular to the first direction. The first hybrid fin extends through and under the first gate structure and the second gate structure, the extending being along the second direction. The second hybrid fin is between the first gate structure and the second gate structure. The second hybrid fin has: a first sidewall that abuts the first gate structure; and a second sidewall that abuts the second gate structure.

公开(公告)号：US20230018721A1

公开(公告)日：2023-01-19

申请号：US17875468

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan HUANG ,  Chia-En HUANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yih WANG

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/112 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

公开(公告)号：US20220336220A1

公开(公告)日：2022-10-20

申请号：US17809847

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu WANG ,  Zhi-Chang LIN ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

公开(公告)号：US20220328497A1

公开(公告)日：2022-10-13

申请号：US17851675

申请日：2022-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yasutoshi OKUNO ,  Jiun-Jia HUANG

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.

公开(公告)号：US20220320280A1

公开(公告)日：2022-10-06

申请号：US17480108

申请日：2021-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.

公开(公告)号：US20220320089A1

公开(公告)日：2022-10-06

申请号：US17476136

申请日：2021-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work functional layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work functional layer fully fills spaces between the second channel nanostructures.