公开(公告)号：US20140098908A1

公开(公告)日：2014-04-10

申请号：US14046479

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： SUNDARRAJAN RANGACHARI ,  Jaiganesh Balakrishnan

IPC: H04L25/06

CPC classification number: H04L25/061

Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.

Abstract translation: 数字电路包括至少一个输入节点，偏置电路和数字基带电路。 输入节点接收包括多个采样实例的采样的数字信号，采样包括正采样和负采样并由第一多个位表示。 偏置电路通过向数字信号添加偏置值来产生偏置数字信号，以分别将正采样和负采样改变为第一采样和第二采样，并由第二多位表示。 数字基带电路被配置为接收和处理偏置的数字信号，使得基于第二多个位中的多个比特切换小于第一多个比特中的比特切换的数量来实现减少的电流消耗。

公开(公告)号：US20250047531A1

公开(公告)日：2025-02-06

申请号：US18651130

申请日：2024-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Aswath VS ,  Sriram Murali ,  Sreenath Narayanan Potty ,  Raju Kharataram Chaudhari ,  Kapil Kumar

IPC: H04L25/03 ,  H04L27/26

Abstract: An example apparatus described herein to implement cancellation pulse generation includes a first memory storing first subsets of data samples of a single pulse cancellation waveform. The example apparatus includes a second memory storing second subsets of data samples of the single pulse cancellation waveform, the second subsets including different data samples of the single pulse cancellation waveform than the first subsets. The example apparatus includes first circuitry coupled to the first memory and to the second memory in parallel. The example apparatus includes a plurality of buffers. The example apparatus includes second circuitry coupled to the plurality of buffers.

公开(公告)号：US12057854B2

公开(公告)日：2024-08-06

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

公开(公告)号：US11757475B2

公开(公告)日：2023-09-12

申请号：US17492710

申请日：2021-10-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan ,  Sriram Murali ,  Sundarrajan Rangachari ,  Yeswanth Guntupalli

IPC: H04B1/10 ,  H04B1/00

CPC classification number: H04B1/0025 ,  H04B1/001 ,  H04B1/0042

Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sin c response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sin c filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

公开(公告)号：US11689316B2

公开(公告)日：2023-06-27

申请号：US17462055

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay Pennam ,  Vamsi Krishna Kandalla ,  Brahmendra Reddy Yatham ,  Shailesh Wardhen ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu

IPC: H04L1/00 ,  H04B1/04

CPC classification number: H04L1/0044 ,  H04B1/04 ,  H04L1/0042 ,  H04L1/0047 ,  H04L1/0061

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

公开(公告)号：US11533068B1

公开(公告)日：2022-12-20

申请号：US17462145

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Rahul Sharma ,  Karthikeyan Gunasekaran ,  Sarma Sundareswara Gunturi ,  Ram Narayan Krishna Nama Mony ,  Jaiganesh Balakrishnan ,  Sandeep Kesrimal Oswal ,  Visvesvaraya Pentakota

IPC: H04L5/12 ,  H04L23/02 ,  H04B1/00 ,  H04B1/30

Abstract: A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

公开(公告)号：US11509291B2

公开(公告)日：2022-11-22

申请号：US16351357

申请日：2019-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Jaiganesh Balakrishnan

IPC: H03H17/06 ,  H03H15/00 ,  H03H17/02

Abstract: A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L−1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.

公开(公告)号：US20220229961A1

公开(公告)日：2022-07-21

申请号：US17411262

申请日：2021-08-25

Applicant: Texas Instruments Incorporated

Inventor： Ajai Paulose ,  Aravind Ganesan ,  Sashidharan Venkatraman ,  Jaiganesh Balakrishnan

IPC: G06F30/34 ,  G06F16/174

Abstract: A system for programming an eFuse array in an integrated circuit (IC) includes an eFuse data file which has a first plurality of bits. The system includes a data compression module which has an input coupled to receive the eFuse data file. The data compression module reduces the size of the eFuse data file and provides a compressed data file. The compressed data file has fewer bits than the eFuse data file. The system includes an eFuse controller which has an input coupled to receive the compressed data file. The eFuse controller programs the eFuse array to permanently store the compressed data file in the eFuse array.

公开(公告)号：US11029919B2

公开(公告)日：2021-06-08

申请号：US16852710

申请日：2020-04-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Suvam Nandi ,  Pooja Sundar ,  Jaiganesh Balakrishnan

IPC: G06F7/523 ,  G06F7/50 ,  H03D7/16

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

公开(公告)号：US10852402B2

公开(公告)日：2020-12-01

申请号：US15834178

申请日：2017-12-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhash Chandra Venkata Sadhu ,  Bharath Patil ,  Jaiganesh Balakrishnan

IPC: G01S7/4865 ,  G01S17/89 ,  G01S7/484 ,  G01S7/486 ,  G01S17/10 ,  G01S7/4911 ,  G01S17/34

Abstract: A three dimensional time of flight (TOF) camera includes a transmitter and a receiver. The transmitter is configured to generate an electrical transmit signal at a plurality of frequencies over an integration time period and generate a transmit optical waveform corresponding with the electrical transmit signal. The receiver is configured to receive a reflected optical waveform that is the transmit optical waveform reflected off of an object, integrate the reflected optical waveform over the integration time period, and determine a distance to the target object based on a TOF of the optical waveform. The integration time period includes exposure time periods. A length of each of the exposure time periods corresponds to one of the frequencies. The TOF is determined based on a correlation of the electrical transmit signal and the return optical waveform utilizing a correlation function with respect to the integration time period.