公开(公告)号：US11063207B2

公开(公告)日：2021-07-13

申请号：US16589157

申请日：2019-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.

公开(公告)号：US11011210B2

公开(公告)日：2021-05-18

申请号：US16592734

申请日：2019-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

IPC: G11C5/06 ,  H01L27/24 ,  H01L27/22

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

公开(公告)号：US20210135092A1

公开(公告)日：2021-05-06

申请号：US16698924

申请日：2019-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Hung-Yueh Chen ,  Yu-Ping Wang ,  Jia-Rong Wu ,  Rai-Min Huang ,  Ya-Huei Tsai ,  I-Fan Chang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.

公开(公告)号：US20210126191A1

公开(公告)日：2021-04-29

申请号：US16689100

申请日：2019-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Chen-Yi Weng ,  Si-Han Tsai ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

公开(公告)号：US20210065750A1

公开(公告)日：2021-03-04

申请号：US16592734

申请日：2019-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

IPC: G11C5/06 ,  H01L27/22 ,  H01L27/24

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.