公开(公告)号：US07666739B2

公开(公告)日：2010-02-23

申请号：US11614048

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/792

摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

公开(公告)号：US20090306169A1

公开(公告)日：2009-12-10

申请号：US11992913

申请日：2006-10-05

申请人： Philip E. Brandish ,  Timothy Sparey ,  Alister Campbell ,  Andrew Pike ,  Nicholas Brandon ,  Wei Zheng

发明人： Philip E. Brandish ,  Timothy Sparey ,  Alister Campbell ,  Andrew Pike ,  Nicholas Brandon ,  Wei Zheng

IPC分类号： A61K31/407 ,  C07D491/044 ,  C07D495/04 ,  A61K31/381

CPC分类号： A61K31/33

摘要： The present invention provides the use of fused pyrrole carboxylic acids of formula (I) for the manufacture of a medicament to inhibit D-amino acid oxidase, particularly for the treatment of neurodegenerative and psychiatric disorders or diseases; certain compounds of formula I being novel, pharmaceutical compositions containing them, their use in medicine and methods of treatment using them are also disclosed.

摘要翻译： 本发明提供式（I）的稠合吡咯羧酸用于制备抑制D-氨基酸氧化酶，特别是用于治疗神经变性和精神疾病或疾病的药物的用途; 某些式I化合物是新型的，含有它们的药物组合物，它们在医药中的用途以及使用它们的治疗方法。

公开(公告)号：US07622373B2

公开(公告)日：2009-11-24

申请号：US11615563

申请日：2006-12-22

申请人： Wei Zheng ,  Chungho Lee

发明人： Wei Zheng ,  Chungho Lee

IPC分类号： H01L21/425

CPC分类号： H01L29/792 ,  H01L21/7624

摘要： A memory device includes a substrate, a first gate stack overlying the substrate, a second gate stack overlying the substrate and spaced apart from the first gate stack, an oxide region formed at a first depth within the substrate and between the first and second gate stacks, and an impurity doped region formed at a second depth within the substrate and between the first and second gate stacks, the first depth being lower than the second depth.

摘要翻译： 存储器件包括衬底，覆盖衬底的第一栅极堆叠，覆盖衬底并与第一栅极堆叠隔开的第二栅极堆叠，形成在衬底内的第一深度处以及在第一和第二栅极堆叠之间的氧化物区域 以及杂质掺杂区域，其形成在衬底内的第二深度处，并且在第一和第二栅极堆叠之间，第一深度低于第二深度。

公开(公告)号：US07573103B1

公开(公告)日：2009-08-11

申请号：US11855704

申请日：2007-09-14

申请人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

发明人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

IPC分类号： H01L27/06

CPC分类号： H01L27/0266 ,  H01L27/0255

摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.

摘要翻译： 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN二极管包括连接到地的p型衬底，在p型衬底中形成的与p型衬底直接物理接触的n型材料的阱，并通过第一金属电连接到p型衬底 线，在n型材料的第一阱中形成的p型材料的阱，形成在p型材料的阱中的第一n型区，与p型材料的阱直接物理接触并连接到 存储器件的字线和形成在n型材料的阱中的与n型材料的阱直接物理接触并且经由第二p型材料电连接到p型材料的阱的第一p型区域 金属线。 PNP二极管包括连接到地的n型衬底，形成在n型衬底中的p型材料的阱与n型衬底直接物理接触并且经由第一金属电连接到n型衬底 线，在p型材料的第一阱中形成的n型材料的阱，形成在n型材料的阱中的与n型材料的阱直接物理接触的第一p型区，并连接到 存储器件的字线和形成在p型材料的阱中的第一n型区域，其与p型材料的阱直接物理接触并且经由第二类型的n型材料电连接到n型材料的阱 金属线。

公开(公告)号：US07492001B2

公开(公告)日：2009-02-17

申请号：US11086310

申请日：2005-03-23

申请人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

发明人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

IPC分类号： H01L29/788 ,  H01L29/72

CPC分类号： H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

摘要翻译： 存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。 存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。 存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极 形成在电介质材料层上。

公开(公告)号：US07463525B2

公开(公告)日：2008-12-09

申请号：US11615280

申请日：2006-12-22

申请人： Wei Zheng ,  Meng Ding ,  Sung-Chul Lee

发明人： Wei Zheng ,  Meng Ding ,  Sung-Chul Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C11/5642 ,  G11C16/0491 ,  G11C16/3454 ,  G11C16/349

摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.

摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，选择目标存储单元，并在其字线和位线上建立适当的编程电压。 阵列中未选择的字线偏置有轻微的负偏置电压，以减少或消除否则可能通过存储器单元传导的泄漏位线电流。 在验证操作（程序验证，软程序验证，擦除验证）和读取操作期间，也可以向未选择的单元施加轻微的负字线偏置电压，以减少或消除可能在验证和读取操作中引入错误的泄漏电流。

公开(公告)号：US07402868B2

公开(公告)日：2008-07-22

申请号：US10976816

申请日：2004-11-01

申请人： Ihsan Jahed Djomehri ,  Mark Randolph ,  Yi He ,  Wei Zheng

发明人： Ihsan Jahed Djomehri ,  Mark Randolph ,  Yi He ,  Wei Zheng

IPC分类号： H01L23/62

CPC分类号： H01L27/115 ,  H01L27/0288

摘要： A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.

摘要翻译： 半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

公开(公告)号：US20080151634A1

公开(公告)日：2008-06-26

申请号：US11615280

申请日：2006-12-22

申请人： Wei Zheng ,  Meng Ding ,  Sung-Chul Lee

发明人： Wei Zheng ,  Meng Ding ,  Sung-Chul Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5642 ,  G11C16/0491 ,  G11C16/3454 ,  G11C16/349

摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.

摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，选择目标存储单元，并在其字线和位线上建立适当的编程电压。 阵列中未选择的字线偏置有轻微的负偏置电压，以减少或消除否则可能通过存储器单元传导的泄漏位线电流。 在验证操作（程序验证，软程序验证，擦除验证）和读取操作期间，也可以向未选择的单元施加轻微的负字线偏置电压，以减少或消除可能在验证和读取操作中引入错误的泄漏电流。

公开(公告)号：US07164046B1

公开(公告)日：2007-01-16

申请号：US11336004

申请日：2006-01-20

申请人： Hari Babu Sunkara ,  Howard C. Ng ,  Wei Zheng ,  Zhihong Wu

发明人： Hari Babu Sunkara ,  Howard C. Ng ,  Wei Zheng ,  Zhihong Wu

IPC分类号： C07C43/11 ,  C08J3/26

CPC分类号： C08G65/34 ,  C08G65/46

摘要： The present invention relates to a process of manufacture of polytrimethylene ether glycol, in which one or more inorganic compounds selected from an inorganic salt and an inorganic base is utilized during certain purification steps to reduce phase separation time.

摘要翻译： 本发明涉及一种制备聚三亚甲基醚二醇的方法，其中在某些纯化步骤中使用一种或多种选自无机盐和无机碱的无机化合物以减少相分离时间。

公开(公告)号：US20060226468A1

公开(公告)日：2006-10-12

申请号：US11101783

申请日：2005-04-07

申请人： Wei Zheng

发明人： Wei Zheng

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L29/7923

摘要： A multi-bit memory cell (200) with a control gate (220) for controlling a middle portion of a channel region (208) provides improved operation including faster programming at smaller voltages and currents. The memory cell (200) includes a source (204) and a drain (206) diffused into a substrate (202) forming a channel region (208) therebetween. A first charge storing layer (214), a second charge storing layer (216) and the control gate (220) are formed on the substrate (202) over the channel region (208) and a gate (218) is formed over the source (204), the drain (206), the first and second charge storing layers (214, 216) and the control gate (220). Dielectric material (210, 212, 224, 226, 228) separates the source (204) and the drain (206) from the gate (218), and the control gate (220) from the first charge storing layer (214), the second charge storing layer (216) and the gate (218).

摘要翻译： 具有用于控制通道区域（208）的中间部分的控制栅极（220）的多位存储器单元（200）提供改进的操作，包括在更小的电压和电流下更快的编程。 存储单元（200）包括扩散到形成其间的沟道区（208）的衬底（202）中的源极（204）和漏极（206）。 在沟道区（208）上的衬底（202）上形成第一电荷存储层（214），第二电荷存储层（216）和控制栅极（220），并且栅极（218）形成在源极 （204），漏极（206），第一和第二电荷存储层（214,216）和控制栅极（220）。 绝缘材料（210,212,224,226,228）将源极（204）和漏极（206）与栅极（218）分开，并且控制栅极（220）从第一电荷存储层（214）， 第二电荷存储层（216）和栅极（218）。