公开(公告)号：US08513703B2

公开(公告)日：2013-08-20

申请号：US12908514

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L21/338 ,  H01L29/778

CPC classification number: H01L29/0661 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Abstract translation: 组III-N HEMT的Si衬底形成为限定将Si衬底的上部区域与Si衬底的下部区域电隔离的p-n结的层。 结果，Si衬底的上部区域可以电浮动，从而获得全缓冲击穿电压，而Si衬底的下部区域可以通过导电环氧树脂附着到封装上，从而显着提高导热性 的III-N HEMT组，并且使不期望的浮动电压区域最小化。

公开(公告)号：US20130015535A1

公开(公告)日：2013-01-17

申请号：US13348577

申请日：2012-01-11

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea ,  Sandeep R. Bahl

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea ,  Sandeep R. Bahl

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

Abstract translation: 沿着半导体主体的上表面设置的非对称绝缘栅场效应晶体管（100U或102U）包含由沟道区（244或284）横向隔开的第一和第二源/漏区（240和242或280和282） 的晶体管的主体材料。 栅电极（262或302）覆盖在沟道区上方的栅介电层（260或300）。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分（250或290）在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置（PH-1-PH-3）处达到多个局部最大值（316-1-316-3）。 通常实施定制，使得袋部分的垂直掺杂剂分布在上半导体表面附近相对平坦。 结果，晶体管具有减小的漏电流。

公开(公告)号：US20120299097A1

公开(公告)日：2012-11-29

申请号：US13177552

申请日：2011-07-06

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的物体 - 物质位置之前至少增加10倍，不超过上部的10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US08309420B1

公开(公告)日：2012-11-13

申请号：US13195833

申请日：2011-08-01

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/88

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material region (108 or 308) of a selected conductivity type. The regions respectively meet overlying zones (104 and 304) of the opposite conductivity type. The concentration of the well dopant reaches a maximum in each body-material region no more than 10 times deeper below the upper semiconductor surface than the overlying zone's depth, decreases by at least a factor of 10 in moving from the empty-well maximum-concentration location through the overlying zone to the upper semiconductor surface, and increases, or decreases by less than a factor of 10, in moving from the filled-well maximum-concentration location through the other zone to the upper semiconductor surface.

Abstract translation: 半导体结构设置有（i）在井的顶部附近具有相对少的阱掺杂物的空阱，以及（ii）在阱的顶部附近具有相当好的掺杂剂的填充阱。 每个孔由所选择的导电类型的对应的主体材料区域（108或308）限定。 这些区域分别满足相反导电类型的覆盖区域（104和304）。 在上半导体表面以上的深层中，阱体掺杂物的浓度达到最大值，在上半导体表面的深度以上10倍以下，在空孔最大浓度的移动中，至少10倍 通过覆盖区域到上半导体表面的位置，并且从填充井最大浓度位置通过另一区域移动到上半导体表面时增加或减小小于10倍。

公开(公告)号：US20120273880A1

公开(公告)日：2012-11-01

申请号：US12912612

申请日：2010-10-26

Applicant: Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L27/088 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.1 μm deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

公开(公告)号：US08258026B2

公开(公告)日：2012-09-04

申请号：US13298284

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）具有用于实现高性能的空井区域。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地基本上单调减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US20120098036A1

公开(公告)日：2012-04-26

申请号：US12908514

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/0661 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Abstract translation: 组III-N HEMT的Si衬底形成为限定将Si衬底的上部区域与Si衬底的下部区域电隔离的p-n结的层。 结果，Si衬底的上部区域可以电浮动，从而获得全缓冲击穿电压，而Si衬底的下部区域可以通过导电环氧树脂附着到封装上，从而显着提高导热性 的III-N HEMT组，并且使不期望的浮动电压区域最小化。

公开(公告)号：US20120098035A1

公开(公告)日：2012-04-26

申请号：US12908458

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

Abstract: The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Abstract translation: 通过在p型Si衬底中形成n阱以直接位于III-NHEMT族金属漏极区的下方，在p型Si衬底上的III-N HEMT组的缓冲击穿显着增加。 n阱形成在击穿期间变得反向偏置的p-n结，从而通过p-n结的反向偏置击穿电压增加缓冲器击穿，并允许衬底接地。 III-N型HEMT的缓冲层也可以注入与p-n结对准的n型和p型掺杂剂，以最小化衬底和缓冲层之间的接合处的任何漏电流。

公开(公告)号：US08129262B1

公开(公告)日：2012-03-06

申请号：US12607041

申请日：2009-10-27

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L21/04

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: Fabrication of an insulated-gate field-effect transistor (110) entails separately introducing three body-material dopants, typically through an opening in a mask, into body material (50) of a semiconductor body so as to reach respective maximum dopant concentrations at three different vertical locations in the body material. A gate electrode (74) is subsequently defined after which a pair of source/drain zones (60 and 62), each having a main portion (60M or 80M) and a more lightly doped lateral extension (60E or 62E), are formed in the semiconductor body. An anneal is performed during or subsequent to introduction of semiconductor dopant that defines the source/drain zones. The body material is typically provided with at least one more heavily doped halo pocket portion (100 and 102) along the source/drain zones. The vertical dopant profile resulting from the body-material dopants alleviates punchthrough and reduces current leakage.

Abstract translation: 绝缘栅场效应晶体管（110）的制造需要通常将三个体材料掺杂剂（通常通过掩模中的开口）引入半导体主体的主体材料（50）中，以便在三层中达到各自的最大掺杂剂浓度 不同垂直位置的身材。 随后限定栅电极（74），之后在每一个具有主要部分（60M或80M）和更轻掺杂的侧向延伸部（60E或62E）的一对源极/漏极区域（60和62）上形成 半导体体。 在引入定义源极/漏极区的半导体掺杂剂期间或之后进行退火。 主体材料通常沿着源极/漏极区域设置有至少一个更重掺杂的卤素口袋部分（100和102）。 由体材料掺杂物产生的垂直掺杂剂分布减轻穿透并减少电流泄漏。

公开(公告)号：US08034679B1

公开(公告)日：2011-10-11

申请号：US12896801

申请日：2010-10-01

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone, normally serving as the drain, and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262) normally serving as the source.

Abstract translation: 制造绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480） 以便在其源极/漏极区的一个（104或264）下方具有低破坏的垂直掺杂剂轮廓，用于减小通常用作漏极的源极/漏极区之间的pn结的寄生电容以及相邻的主体材料（108 或268）。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的物体 - 物质位置之前至少增加10倍，不超过上部的10倍 半导体表面比该源/漏区。 主体材料优选地设置有沿着通常用作源的另一个源极/漏极区（102或262）设置的更重掺杂的口袋部分（120或280）。