公开(公告)号：US20060284880A1

公开(公告)日：2006-12-21

申请号：US11157657

申请日：2005-06-21

申请人： Kun Zhou ,  Xi Wang ,  Baining Guo ,  Heung-Yeung Shum

发明人： Kun Zhou ,  Xi Wang ,  Baining Guo ,  Heung-Yeung Shum

IPC分类号： G09G5/00

CPC分类号： G06T15/04

摘要： Texture montage is described. In one aspect, feature correspondences are received. The feature correspondences map at least one region on a 3-D mesh to at least one region on an image of one or more images. Each of the images provides texture information. An atlas of texture patches is created based on the feature correspondences. The atlas of texture patches provides for rendering texture from the images onto the 3-D mesh.

摘要翻译： 纹理蒙太奇被描述。 在一个方面，接收到特征对应。 特征对应将三维网格上的至少一个区域映射到一个或多个图像的图像上的至少一个区域。 每个图像提供纹理信息。 基于特征对应创建纹理补丁的图集。 纹理贴图的图集用于将图像中的纹理渲染到3-D网格上。

公开(公告)号：US20050280648A1

公开(公告)日：2005-12-22

申请号：US10990244

申请日：2004-11-15

申请人： Xi Wang ,  Xin Tong ,  Stephen Lin ,  Baining Guo ,  Heung-Yeung Shum

发明人： Xi Wang ,  Xin Tong ,  Stephen Lin ,  Baining Guo ,  Heung-Yeung Shum

IPC分类号： G06T15/20 ,  G06T15/50 ,  G06T15/60 ,  G06T17/00 ,  G09G5/00

CPC分类号： G06T15/04

摘要： A “mesostructure renderer” uses pre-computed multi-dimensional “generalized displacement maps” (GDM) to provide real-time rendering of general non-height-field mesostructures on both open and closed surfaces of arbitrary geometry. In general, the GDM represents the distance to solid mesostructure along any ray cast from any point within a volumetric sample. Given the pre-computed GDM, the mesostructure renderer then computes mesostructure visibility jointly in object space and texture space, thereby enabling both control of texture distortion and efficient computation of texture coordinates and shadowing. Further, in one embodiment, the mesostructure renderer uses the GDM to render mesostructures with either local or global illumination as a per-pixel process using conventional computer graphics hardware to accelerate the real-time rendering of the mesostructures. Further acceleration of mesostructure rendering is achieved in another embodiment by automatically reducing the number of triangles in the rendering pipeline according to a user-specified threshold for acceptable texture distortion.

摘要翻译： “mesostructure渲染器”使用预先计算的多维“广义位移图”（GDM），以便在任意几何的开放和闭合表面上提供一般非高度场介观结构的实时渲染。 一般来说，GDM表示沿着体积样品内的任何点的任何射线投射到固体介观结构的距离。 给定预先计算的GDM，然后，介观结构渲染器在对象空间和纹理空间中联合计算介观结构可见度，从而实现纹理失真的控制和纹理坐标和阴影的有效计算。 此外，在一个实施例中，使用传统计算机图形硬件的介面结构渲染器使用GDM来渲染具有局部或全局照明的介观结构作为每像素处理，以加速介观结构的实时渲染。 在另一个实施例中，通过根据用户指定的可接受纹理失真的阈值自动减少渲染流水线中的三角形数量来实现进一步加速的介观结构渲染。

公开(公告)号：US09953118B2

公开(公告)日：2018-04-24

申请号：US13696437

申请日：2011-09-25

申请人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Zhan Chai ,  Xi Wang

发明人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Zhan Chai ,  Xi Wang

IPC分类号： G06F17/10 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： The present invention provides a modeling method of a SPICE model series of a Silicon On Insulator (SOI) Field Effect Transistor (FET), where auxiliary devices are designed and fabricated, electrical property data is measured, intermediate data is obtained, model parameters are extracted based on the intermediate data, a SPICE model of an SOI FET of a floating structure is established, model parameters are extracted by using the intermediate data and data of the auxiliary devices, a macro model is complied, and a SPICE model of an SOI FET of a body leading-out structure is established. The modeling method provided in the present invention takes an influence of a parasitic transistor of a leading-out part in a body leading-out structure into consideration, and model series established by using the method can more accurately reflect actual operating conditions and electrical properties of the SOI FET of a body leading-out structure and the SOI FET of a floating structure, thereby improving fitting effects of the models.

公开(公告)号：US09299556B2

公开(公告)日：2016-03-29

申请号：US13976486

申请日：2010-12-31

申请人： Xing Wei ,  Zhongdang Wang ,  Fei Ye ,  Gongbai Cao ,  Chenglu Lin ,  Miao Zhang ,  Xi Wang

发明人： Xing Wei ,  Zhongdang Wang ,  Fei Ye ,  Gongbai Cao ,  Chenglu Lin ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L21/02 ,  H01L21/322 ,  H01L21/762

CPC分类号： H01L21/3226 ,  H01L21/76254

摘要： A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.

摘要翻译： 通过沟槽工艺制备具有掩埋绝缘层的半导体衬底的方法包括以下步骤：提供器件衬底和支撑衬底; 在所述器件基板的表面上形成绝缘层; 在所述器件基板上进行加热处理，以在所述器件基板的表面上形成剥离区域; 将具有绝缘层的器件基板与支撑基板接合，使得绝缘层夹在器件基板和支撑基板之间; 退火和加强粘合界面，使得接合界面的粘附水平满足以下倒角研磨，减薄和抛光工艺中的要求; 在接合的器件基板上进行倒角研磨，变薄和抛光工艺。

公开(公告)号：US09134361B2

公开(公告)日：2015-09-15

申请号：US13696455

申请日：2011-09-25

申请人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Zhan Chai ,  Xi Wang

发明人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Zhan Chai ,  Xi Wang

IPC分类号： G06F7/60 ,  G01R31/26 ,  G06F17/50

CPC分类号： G01R31/2628 ,  G01R31/2603 ,  G06F17/5036

摘要： The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps. In the present invention, proper test curves are successively selected according to model equations, and various kinds of parameters are successively determined, thereby accurately and effectively extracting the DC parameters of the BSIMSOI4 model.

摘要翻译： 本发明提供了一种用于确定BSIMSOI4直流（DC）模型参数的方法，其中，体内引出结构和不同尺寸的多个金属氧化物半导体场效应晶体管（MOSFET）器件和多个MOSFET器件 提供浮动结构和不同尺寸; 所有MOSFET器件的Id-Vg-Vp，Id / Ip-Vd-Vg，Ig-Vg-Vd，Ig-Vp，Ip-Vg-vd，Is / Id-Vp和Id / Ip-Vp-Vd特性 测量浮体结构的所有MOSFET器件的体导体结构和Id-Vg-Vp，Id-Vd-Vg和Ig-Vg-Vd特性; 获得不具有体引出结构的每个MOSFET器件和浮置结构的每个MOSFET器件的自发热效应的电性能曲线; 然后根据具体步骤依次提取BSIMSOI4模型的DC参数。 在本发明中，根据模型方程依次选择适当的试验曲线，并连续确定各种参数，从而准确有效地提取BSIMSOI4型号的直流参数。

公开(公告)号：US08937354B2

公开(公告)日：2015-01-20

申请号：US13128907

申请日：2010-09-08

申请人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/266 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42384 ,  H01L21/266 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/78612

摘要： The present invention discloses a PD SOI device with a body contact structure. The active region of the PD SOI device includes: a body region; a gate region, which is inverted-L shaped, formed on the body region; a N-type source region and a N-type drain region, formed respectively at the two opposite sides of the anterior part the body region; a body contact region, formed at one side of the posterior part of the body region, which is side-by-side with the N-type source region; and a first silicide layer, formed on the body contact region and the N-type source region, which is contact to both of the body contact region and the N-type source region. The body contact region of the device is formed on the border of the source region and the leading-out terminal of the gate electrode. It can suppress floating body effect of the PD SOI device meanwhile not increasing the chip area, thereby overcoming the shortcoming in the prior art that the chip area is enlarged when the traditional body contact structure is employed. Furthermore, the fabrication process provided herein is simple and compatible to the CMOS technology.

摘要翻译： 本发明公开了一种具有体接触结构的PD SOI器件。 PD SOI器件的有源区包括：主体区域; 形成在身体区域上的倒L形的栅极区域; 分别形成在身体区域的前部的两个相对侧的N型源极区域和N型漏极区域; 身体接触区域，形成在与N型源区并排的身体区域的后部的一侧; 以及形成在与所述本体接触区域和所述N型源极区域接触的所述本体接触区域和所述N型源极区域上的第一硅化物层。 器件的体接触区域形成在栅极电极的源极区域和引出端子的边界上。 它可以抑制PD SOI器件的浮体效应，同时不增加芯片面积，从而克服了现有技术中使用传统的体接触结构时芯片面积扩大的缺点。 此外，本文提供的制造工艺简单且与CMOS技术兼容。

公开(公告)号：US08710549B2

公开(公告)日：2014-04-29

申请号：US13128439

申请日：2010-09-07

申请人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

发明人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

IPC分类号： H01L29/66

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/78612

摘要： A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

摘要翻译： 公开了一种用于消除浮体效应和自发热效应的SOI MOS器件。 该器件包括将有源栅极沟道耦合到Si衬底的连接层。 连接层在设备操作期间提供电气和热通道，可以消除浮体效应和自热效应。 详细公开了在Si活性通道和Si衬底之间具有SiGe连接器的MOS器件的实例，并提供制造工艺。

公开(公告)号：US08699518B2

公开(公告)日：2014-04-15

申请号：US12905147

申请日：2010-10-15

申请人： Xi Wang ,  Qiong Zhang ,  Paparao Palacharla ,  Takao Naito

发明人： Xi Wang ,  Qiong Zhang ,  Paparao Palacharla ,  Takao Naito

IPC分类号： H04J3/16

CPC分类号： H04J14/0267 ,  H04J14/0241 ,  H04J14/0257

摘要： A system and method are provided for dynamically reconfiguring an optical circuit between a first node and a second node of a communication network. The system and method may include establishing a scheduling window for receiving a plurality of optical traffic demands, classifying the plurality of optical traffic demands into at least a set of bandwidth adjustable demands and a set of fixed bandwidth demands, provisioning a first set of provisioned wavelengths from the plurality of wavelengths to carry the set of fixed bandwidth demands during the scheduling window, allocating the bandwidth remaining on the first set of provisioned wavelengths to the set of bandwidth adjustable demands, and if necessary, provisioning a second set of provisioned wavelengths from the plurality of wavelengths to carry the bandwidth required by the set of bandwidth adjustable demands that could not be allocated to the first set of provisioned wavelengths.

摘要翻译： 提供了一种用于在通信网络的第一节点和第二节点之间动态重新配置光电路的系统和方法。 该系统和方法可以包括建立用于接收多个光学业务​​需求的调度窗口，将多个光学业务​​需求分类为至少一组带宽可调节需求和一组固定带宽需求，提供第一组供应波长 从所述多个波长在所述调度窗口期间携带所述固定带宽需求集合，将所述第一组所设置的波长上剩余的带宽分配给所述带宽可调节需求集合，并且如果需要，从所述多个波长中提供第二组所提供的波长 多个波长以承载不能分配给第一组所配置的波长的一组带宽可调节需求所需的带宽。

公开(公告)号：US08667440B2

公开(公告)日：2014-03-04

申请号：US13696401

申请日：2011-09-23

申请人： Zhan Chai ,  Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

发明人： Zhan Chai ,  Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  H01L22/20

摘要： A calibration method for a device using TCAD to emulation SOI field effect transistor, where process emulation MOS device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; the process emulation MOS device structures are calibrated according to a TEM test result, a SIMS test result, a CV test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Thereby, providing effective guidance for research, development and optimization of a new process flow are realized.

摘要翻译： 一种使用TCAD仿真SOI场效应晶体管的器件的校准方法，其中通过建立TCAD过程仿真程序获得具有不同通道长度Lgate的工艺仿真MOS器件结构; 根据TEM测试结果，SIMS测试结果，CV测试结果，WAT测试结果和实际设备的方形电阻测试结果对过程仿真MOS器件结构进行校准，从而完成关键的TCAD仿真校准 SOI场效应晶体管的电参数。 从而实现了对新工艺流程的研究，开发和优化的有效指导。

公开(公告)号：US20140052414A1

公开(公告)日：2014-02-20

申请号：US14112535

申请日：2011-05-10

申请人： Qingguo Xie ,  Peng Xiao ,  Xi Wang ,  Na Li ,  Yuanbao Chen ,  Wei Liu

发明人： Qingguo Xie ,  Peng Xiao ,  Xi Wang ,  Na Li ,  Yuanbao Chen ,  Wei Liu

IPC分类号： G01T1/20

CPC分类号： G01T1/2006 ,  G01T1/17

摘要： A method for extracting scintillation pulse information includes followed steps: 1. obtaining a peak value of the scintillation pulse in a certain energy spectrum, and setting at least three threshold voltages according to the peak value; 2. determining the time when the scintillation pulse passes through the each threshold voltage, wherein each time value and its corresponding threshold voltage form a sampling point; 3. selecting multiple sampling points as sampling points for reconstructing and reconstructing pulse waveform; 4. obtaining the data of original scintillation pulse by using reconstructed pulse waveform. A device for extracting scintillation pulse information includes a threshold voltage setting module (100), a time sampling module (200), a pulse reconstruction module (300) and an information acquiring module (400).

摘要翻译： 提取闪烁脉冲信息的方法包括以下步骤：1.获得特定能谱中的闪烁脉冲的峰值，并根据峰值设定至少三个阈值电压; 2.确定闪烁脉冲通过每个阈值电压的时间，其中每个时间值及其相应的阈值电压形成采样点; 3.选择多个采样点作为重建和重构脉搏波形的采样点; 4.通过重建脉冲波形获得原始闪烁脉冲的数据。 用于提取闪烁脉冲信息的装置包括阈值电压设定模块（100），时间采样模块（200），脉冲重建模块（300）和信息获取模块（400）。