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公开(公告)号：US20100245328A1
公开(公告)日：2010-09-30
申请号：US12734376
申请日：2008-08-21
IPC分类号： G09G5/00
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0876 , G09G2310/0286 , G09G2320/0209 , G09G2320/0219 , G11C19/184
摘要： In a storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, at least one (VSS) of a high-potential supply voltage (VDD) and a low-potential supply voltage (VSS) differs from a supply voltage (GVSS) of a corresponding logical level of the scanning signal line drive circuit, the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage. This makes it possible to achieve a storage capacitor line drive circuit capable of avoiding malfunctioning even in a case where the storage capacitor line drive circuit receives noise from a scanning signal line, and a display device including the storage capacitor line drive circuit.
摘要翻译： 在驱动有源矩阵型显示装置的辅助电容线并由扫描信号线驱动电路的输出驱动的辅助电容线驱动电路中，高电位电源电压（VDD）和低电位 电位电压（VSS）与扫描信号线驱动电路的相应逻辑电平的电源电压（GVSS）不同，高电位电源电压和低电位电源电压用于产生信号电压 前一阶段到产出阶段。 这使得即使在存储电容器线路驱动电路从扫描信号线接收到噪声的情况下也可以实现能够避免故障的存储电容器线路驱动电路，以及包括辅助电容线驱动电路的显示装置。
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公开(公告)号：US20100244946A1
公开(公告)日：2010-09-30
申请号：US12734044
申请日：2008-08-26
IPC分类号： H01L25/00
CPC分类号： G09G3/3677 , G09G3/3655 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G11C19/184 , G11C19/28 , H03K17/063 , H03K17/165 , H03K17/693
摘要： A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.
摘要翻译： 电路由多个n沟道型晶体管构成，所述电路包括：在所述多个晶体管中，包括用于接收VDD电压的漏极端子的晶体管，源极端子和用于接收输入的栅极端子 信号; 在多个晶体管中，包括用于接收VDD的电压的漏极端子，连接到输出端子的源极端子和连接到晶体管的源极端子的栅极端子的晶体管; 以及设置在节点和时钟端子之间用于接收时钟信号的电容器。 在至少一个实施例中，输入到时钟端的时钟信号的频率高于从输出端输出的输出信号的频率。 因此，可以提供：由相同导电类型的晶体管构成的半导体器件，该半导体器件可以通过防止电位电平的降低而输出稳定的信号; 以及包括半导体器件的显示装置。
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公开(公告)号：US20100214206A1
公开(公告)日：2010-08-26
申请号：US12734218
申请日：2008-08-26
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/06 , G09G2330/08 , G11C19/28
摘要： At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.
摘要翻译： 本发明的至少一个实施例是多个单元电路以多级连接，当单元电路同时导通以输出高电平输出信号时，进行正常操作。 当移位寄存器发生故障时，使得由前一级和后级单元电路提供的输出信号同时设置为高电平，故障恢复电路并包括在单元电路中，在至少一个实施例中检测故障。 故障恢复电路向节点提供高电压，从而强制拉下输出信号。 此外，故障恢复电路强制地对另一个节点进行放电，从而释放在电容中累积的电荷。 结果，故障中的移位寄存器可以立即恢复正常运行。 本发明的至少一个实施例适用于诸如显示装置和成像装置的驱动电路等。
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公开(公告)号：US20100141642A1
公开(公告)日：2010-06-10
申请号：US12733119
申请日：2008-05-15
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 高层次。 在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。 因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。
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公开(公告)号：US20090115716A1
公开(公告)日：2009-05-07
申请号：US11921116
申请日：2006-06-12
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0232 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2340/0442 , G11C19/28
摘要： In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.
摘要翻译： 在本发明的一个实施例中，本移位寄存器是设置在显示设备中的移位寄存器，通过该移位寄存器可以获得部分屏幕显示。 移位寄存器包括设置在中间级中的移位停止电路，并且在部分屏幕显示中停止移位寄存器的第一级和最后级之间的移位寄存器的操作。 移位寄存器还包括一个电路，其被提供在除了中间级之外的阶段中，使得该电路不执行信号处理而用作信号路径。 该电路与配置中的换挡停止电路相同。 上述可以改善采用本移位寄存器的显示装置的显示质量。
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公开(公告)号：US20070242021A1
公开(公告)日：2007-10-18
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.
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公开(公告)号：US08248348B2
公开(公告)日：2012-08-21
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175 , H03L5/00 , G09G5/00 , G09G3/28 , G09G3/36
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.
摘要翻译： 电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。 电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器 输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。 利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。
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公开(公告)号：US08174479B2
公开(公告)日：2012-05-08
申请号：US11921116
申请日：2006-06-12
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0232 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2340/0442 , G11C19/28
摘要： In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.
摘要翻译： 在本发明的一个实施例中，本移位寄存器是设置在显示设备中的移位寄存器，通过该移位寄存器可以获得部分屏幕显示。 移位寄存器包括设置在中间级中的移位停止电路，并且在部分屏幕显示中停止移位寄存器的第一级和最后级之间的移位寄存器的操作。 移位寄存器还包括一个电路，其被提供在除了中间级之外的阶段中，使得该电路不执行信号处理而用作信号路径。 该电路与配置中的换挡停止电路相同。 上述可以改善采用本移位寄存器的显示装置的显示质量。
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公开(公告)号：US07289097B2
公开(公告)日：2007-10-30
申请号：US10702077
申请日：2003-11-06
申请人： Seijirou Gyouten , Sachio Tsujino , Hajime Washio , Eiji Matsuda , Keiichi Ina , Yuhichiroh Murakami , Shunsuke Hayashi , Mamoru Onda
发明人： Seijirou Gyouten , Sachio Tsujino , Hajime Washio , Eiji Matsuda , Keiichi Ina , Yuhichiroh Murakami , Shunsuke Hayashi , Mamoru Onda
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2310/0283 , G09G2310/0289 , G11C19/00 , G11C19/28
摘要： The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.
摘要翻译： 本发明公开了一种扫描方向控制电路，其包括双向移位寄存器，其中根据切换信号L / R切换移位方向，当切换信号L / R在比驱动电压低的振幅时由电平移位器升压。 扫描方向控制电路包括电平移位器和双向移位寄存器之间的锁存电路，并且控制电路使得锁存电路在构成双向移位寄存器的触发器的移位操作之后响应于输出而完成锁存操作 触发器的信号。 控制电路在锁存定时之前，之后和之后的时段中使电平移位器进入有效状态，并且在剩余时间段内使电平移位器进入非活动状态。 利用这种布置，可以在低功耗的情况下以预定的时序提供开关信号L / R，而不管其外部输入定时。
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80.发明授权Driving circuit of display device, method of driving display device, and display device for enabling partial screen and widescreen display modes 失效显示装置的驱动电路，驱动显示装置的方法以及用于启用部分屏幕和宽屏显示模式的显示装置公开(公告)号：US08144103B2
公开(公告)日：2012-03-27
申请号：US11921444
申请日：2006-06-12
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G09G2310/0275
摘要： A driving circuit of a display device is disclosed in accordance with an embodiment of the present invention creates a non-display area on a display section of the display device so that a partial-screen display becomes available. The driving circuit includes a shift register and a signal processing circuit that processes a signal tapped off from the shift register. In partial-screen display, the signal processing circuit interrupts a signal tapped off from a predetermined stage of the shift register. This makes it possible to realize a driving circuit of a display device by which a high-quality display is possible with a small circuit area.
摘要翻译： 根据本发明的实施例公开了显示装置的驱动电路，在显示装置的显示部分上创建非显示区域，使得部分屏幕显示变得可用。 驱动电路包括移位寄存器和处理从移位寄存器分接的信号的信号处理电路。 在部分屏幕显示中，信号处理电路中断从移位寄存器的预定级分开的信号。 这使得可以实现具有小电路区域的高质量显示的显示装置的驱动电路。
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