公开(公告)号：US07355239B1

公开(公告)日：2008-04-08

申请号：US11514743

申请日：2006-08-31

Applicant: Barbara Haselden ,  Yi Ding

Inventor： Barbara Haselden ,  Yi Ding

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L21/76224 ,  H01L27/11521 ,  Y02P80/30

Abstract: Improved methods of manufacturing semiconductor devices are provided to reduce dielectric loss in isolation trenches of the devices. In one example, a method of manufacturing a semiconductor device includes forming a plurality of shallow trench isolation (STI) trenches in a substrate. A tunnel oxide layer, a first conductive layer, a gate dielectric layer, and a second conductive layer are formed above the substrate. The layers are etched to delineate a plurality of stacked gate structures. In particular, the etching may include: performing a first etch of the second conductive layer, wherein at least a portion of the second conductive layer above the STI trenches remains following the first etch; and performing a second etch of the second conductive layer, wherein the remaining portion of the second conductive layer above the STI trenches and portions of the gate dielectric layer above the STI trenches are completely removed by the second etch.

Abstract translation: 提供制造半导体器件的改进方法以减少器件隔离沟槽中的介电损耗。 在一个示例中，制造半导体器件的方法包括在衬底中形成多个浅沟槽隔离（STI）沟槽。 在衬底上形成隧道氧化物层，第一导电层，栅极介电层和第二导电层。 蚀刻这些层以描绘多个堆叠的栅极结构。 特别地，蚀刻可以包括：执行第二导电层的第一蚀刻，其中STI沟槽上方的第二导电层的至少一部分保持跟随第一蚀刻; 以及执行所述第二导电层的第二蚀刻，其中所述STI沟槽上方的所述第二导电层的剩余部分和所述STI沟槽上方的所述栅极电介质层的部分通过所述第二蚀刻被完全去除。

公开(公告)号：US07301196B2

公开(公告)日：2007-11-27

申请号：US11112702

申请日：2005-04-22

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed and the floating layer is removed from over at least a portion of the select gate lines. A dielectric (1510) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These protrusions are exploited to define the control gates independently of photolithographic alignment. The floating gates are then defined independently of any photolithographic alignment other than the alignment involved in patterning the substrate isolation regions and the select gate lines. In another aspect, a nonvolatile memory cell has a conductive floating gate (160). A dielectric layer (1510) overlying the floating gate has a continuous feature that overlies the floating gate and also overlies the select gate (140). The control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate but not the select gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在非易失性存储器中，在半导体衬底（120）中形成衬底隔离区（220）。 衬底隔离区域是突出于衬底上方的电介质区域。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区被暴露，并且浮选层从至少一部分选择栅极线上去除。 在浮动栅极层上形成电介质（1510），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些突起被利用来独立于光刻对准来限定控制栅。 然后，浮动栅极独立于除图案化衬底隔离区域和选择栅极线之外的对准的任何光刻对准。 在另一方面，非易失性存储单元具有导电浮动栅极（160）。 覆盖浮置栅极的介电层（1510）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的连续特征。 控制栅极（160）覆盖在电介质层的连续特征上，并且覆盖在浮动栅极而不是选择栅极。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US20070264827A1

公开(公告)日：2007-11-15

申请号：US11431255

申请日：2006-05-09

Applicant: Yi Ding ,  Xinyu Zhang ,  Wee-chen Gan

Inventor： Yi Ding ,  Xinyu Zhang ,  Wee-chen Gan

IPC: H01L21/461 ,  H01L21/302

CPC classification number: H01L21/7684 ,  H01L21/31053 ,  H01L21/3212 ,  H01L27/115 ,  H01L27/11521

Abstract: A method for planarizing a surface in an integrated circuit manufacturing process provides a first film of a first material over a non-uniform surface, such as a surface including isolation trenches. The first material includes, for example, a polysilicon layer to be used to form floating gates in a non-volatile memory integrated circuit. A second film, which is a sacrificial film formed using a second material, such as silicon oxide, is then provided over the first film. Partial removal of the second film is carried out using chemical mechanical polishing until a portion of the first film is exposed using a first slurry that is selective to the first material. Thereafter, the remaining layer of the second film is removed, along with planarization of the surface, using a second slurry that is less selective, i.e., has a selectivity of the first film to the second film that is less than a predetermine value (e.g., 2:1).

Abstract translation: 用于在集成电路制造工艺中平坦化表面的方法在非均匀表面（例如包括隔离沟槽的表面）上提供第一材料的第一膜。 第一材料包括例如用于在非易失性存储器集成电路中形成浮置栅极的多晶硅层。 然后在第一膜上提供第二膜，其是使用第二材料形成的牺牲膜，例如氧化硅。 使用化学机械抛光进行部分去除第二膜，直到使用对第一材料有选择性的第一浆料暴露第一膜的一部分。 此后，使用较少选择性的第二浆料，即第一膜对第二膜的选择性小于预定值（例如，第二膜），除去第二膜的剩余层以及表面的平坦化。 ，2：1）。

公开(公告)号：US07190019B2

公开(公告)日：2007-03-13

申请号：US11013593

申请日：2004-12-14

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/787 ,  H01L29/788 ,  H01L29/336

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11529

Abstract: A widened contact area (170X) of a conductive feature (170) is formed by means of self-alignment between an edge (170E2) of the conductive feature and an edge (140E) of another feature (140). The other feature (“first feature”) is formed from a first layer, and the conductive feature is formed from a second layer overlying the first layer. The edge (170E2) of the conductive feature is shaped to provide a widened contact area. This shaping is achieved in a self-aligned manner by shaping the corresponding edge (140E) of the first feature.

Abstract translation: 通过在导电特征的边缘（170E2）与另一特征（140）的边缘（140E）之间的自对准，形成导电特征（170）的加宽的接触区域（170×）。 另一特征（“第一特征”）由第一层形成，并且导电特征由覆盖第一层的第二层形成。 导电特征的边缘（170E 2）成形为提供加宽的接触面积。 通过使第一特征的对应边缘（140E）成形，以自对准的方式实现该成形。

公开(公告)号：US07101757B2

公开(公告)日：2006-09-05

申请号：US10632155

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

Abstract: In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current.

Abstract translation: 在非易失性存储单元（110）中，选择栅极晶体管形成为埋入沟道晶体管以增加晶体管电流。

公开(公告)号：US07060565B2

公开(公告)日：2006-06-13

申请号：US10631452

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11534

Abstract: A memory cell (110) has a select gate (140) and at least two floating gates (160). A gate dielectric (150) for the floating gates (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of the select gate (140). The dielectric thickness on the select gate is controlled by the dopant concentration in the select gate. Other features are also provided.

Abstract translation: 存储单元（110）具有选择栅极（140）和至少两个浮置栅极（160）。 用于浮动栅极（160）的栅极电介质（150）通过热氧化同时作为选择栅极（140）的表面上的电介质形成。 选择栅极上的电介质厚度由选择栅极中的掺杂剂浓度控制。 还提供其他功能。

公开(公告)号：US07053438B2

公开(公告)日：2006-05-30

申请号：US10972159

申请日：2004-10-21

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed, simultaneously. In a nonvolatile memory having a memory cell with two floating gates, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness.

Abstract translation: 在具有两个浮置栅极的非易失性存储单元的制造中，与选择栅极相同的层（140）形成一个或多个外围晶体管栅极。 同时形成用于这些外围晶体管的栅极电介质（130）和用于选择栅极的栅极电介质（130）。 在具有具有两个浮置栅极的存储单元的非易失性存储器中，用于外围晶体管的栅极电介质（130）和选择栅极（140）的栅极电介质（130）具有相同的厚度。

公开(公告)号：US06995060B2

公开(公告)日：2006-02-07

申请号：US10393202

申请日：2003-03-19

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S438/975

Abstract: A structure is obtained having a semiconductor substrate, the structure having an upward protruding feature (140). A first layer (160) is formed on the structure. The first layer (160) has a first portion (170.1) protruding upward over the protruding feature (140). Then a second layer (1710) is formed over the first layer (160) such that the first portion (170.1) is exposed and not completely covered by the second layer (1710). The first layer (160) is partially removed selectively to the second layer to form a cavity (1810) at the location of the first feature (140). A third layer (1910) is formed in the cavity. Then at least parts of the second layer (1710) and the first layer (160) are removed selectively to the third layer (1910). In some embodiments, self-aligned features are formed from the first layer (160) over the sidewalls of the first features (140) as a result.

Abstract translation: 获得具有半导体衬底的结构，该结构具有向上突出的特征（140）。 在该结构上形成第一层（160）。 第一层160具有在突出特征140上向上突出的第一部分170.1）。 然后在第一层（160）上形成第二层（1710），使得第一部分（170.1）暴露并不完全被第二层（1710）覆盖。 选择性地将第一层（160）部分地移除到第二层以在第一特征（140）的位置处形成空腔（1810）。 在空腔中形成第三层（1910）。 然后，选择性地将第二层（1710）和第一层（160）的至少一部分去除到第三层（1910）。 在一些实施例中，结果是在第一特征（140）的侧壁上从第一层（160）形成自对准特征。

公开(公告)号：US20050220781A1

公开(公告)日：2005-10-06

申请号：US10934861

申请日：2004-09-03

Applicant: Duen-Hwa Yan ,  Yi Ding ,  Li Wang ,  Mien-Chie Hung

Inventor： Duen-Hwa Yan ,  Yi Ding ,  Li Wang ,  Mien-Chie Hung

IPC: A61K38/00 ,  A61K38/48 ,  A61K48/00 ,  C07H21/04 ,  C07K14/47 ,  C12N9/64 ,  C12N15/09

CPC classification number: C07K14/4702 ,  A61K38/00 ,  A61K48/00

Abstract: The present invention regards IFIX proteins, polypeptides, peptides, and the polynucleotides that encode them. In particular embodiments, the IFIX proteins, polypeptides, and/or peptides comprise tumor suppressive, anti-cell proliferative pro-apoptotic and/or cell cycle arrest-inducing activities. In more particular embodiments, these forms are useful for cancer therapy, particularly when administered in combination with liposomes.

Abstract translation: 本发明涉及IFIX蛋白质，多肽，肽和编码它们的多核苷酸。 在具体实施方案中，IFIX蛋白质，多肽和/或肽包括肿瘤抑制，抗细胞增殖性促细胞凋亡和/或细胞周期停滞诱导活性。 在更具体的实施方案中，这些形式可用于癌症治疗，特别是当与脂质体组合施用时。

公开(公告)号：US06928209B2

公开(公告)日：2005-08-09

申请号：US10367268

申请日：2003-02-15

Applicant: Jun Su ,  Yi Ding

Inventor： Jun Su ,  Yi Ding

IPC: G02B6/28 ,  G02B6/34 ,  G02F1/01 ,  H04J14/02

CPC classification number: G02B6/12007 ,  G02B6/2821 ,  G02B6/29338 ,  G02B6/29353 ,  G02B6/29355 ,  G02B6/29383 ,  G02F1/0147 ,  G02F2203/15 ,  G02F2203/585

Abstract: An optical add/drop multiplexer may be formed using ring resonators. In some embodiments, ring resonators may be used instead of Bragg gratings in a Mach-Zehnder interferometer configuration. One or more wavelengths may be added or dropped or a band pass of wavelengths may be added or dropped in a wavelength division multiplexed system.

Abstract translation: 可以使用环形谐振器来形成光分插复用器。 在一些实施例中，可以使用环形谐振器来代替Mach-Zehnder干涉仪配置中的布拉格光栅。 一个或多个波长可以被添加或丢弃，或波长带通可以在波分多路复用系统中被添加或丢弃。