公开(公告)号：US20120045878A1

公开(公告)日：2012-02-23

申请号：US13283331

申请日：2011-10-27

申请人： Naoyoshi Tamura

发明人： Naoyoshi Tamura

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/933

摘要： A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.

公开(公告)号：US20100320546A1

公开(公告)日：2010-12-23

申请号：US12782882

申请日：2010-05-19

申请人： Naoyoshi Tamura

发明人： Naoyoshi Tamura

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/265 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.

摘要翻译： 半导体器件包括MOS晶体管，MOS晶体管上的源电极和漏电极，每个包括第一碳浓度的碳和第一磷浓度的磷和第二碳掺杂硅层的第一碳掺杂硅层， 第一碳化硅层，其包含比第一磷浓度高的第二磷浓度的磷，并且包括第二碳浓度小于或等于第一碳浓度的碳。

公开(公告)号：US20100047978A1

公开(公告)日：2010-02-25

申请号：US12606720

申请日：2009-10-27

申请人： Naoyoshi Tamura

发明人： Naoyoshi Tamura

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/933

摘要： A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：（a）通过栅极绝缘膜在硅衬底上形成栅电极; （b）在硅衬底上形成具有不同蚀刻特性的绝缘膜和牺牲膜的叠层，覆盖栅电极，并各向异性地蚀刻层压，以在栅电极和栅极绝缘膜的侧壁上形成侧壁间隔物 ; （c）在侧壁间隔物的两侧将杂质注入到硅衬底中; （d）蚀刻硅衬底和牺牲膜以在硅衬底中形成凹陷，并且将每个侧壁衬垫的横截面形状改变为大致L形; （e）在凹槽中外延生长含Si-Ge的晶体; 和（f）沉积含有应力的绝缘膜，覆盖侧壁间隔物。

公开(公告)号：US07432180B2

公开(公告)日：2008-10-07

申请号：US11434132

申请日：2006-05-16

申请人： Yasunori Uchino ,  Kazuo Kawamura ,  Naoyoshi Tamura

发明人： Yasunori Uchino ,  Kazuo Kawamura ,  Naoyoshi Tamura

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation film and the silicon region are formed, such that the metallic nickel film covers the insulation film and the silicon region, forming a first nickel silicide layer primarily of a Ni2Si phase on a surface of the silicon region of the metallic nickel film by applying an annealing process to the silicon substrate, removing the metallic nickel film, after the step of forming the first nickel silicide layer, by a selective wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of a NiSi phase by a thermal annealing process conducted in a silane gas.

摘要翻译： 制造半导体器件的方法包括通过自对准工艺在由绝缘膜限定的硅区域上选择性地形成镍单硅化物层的步骤。 自对准工艺包括在其上形成有绝缘膜和硅区域的硅衬底上形成金属镍膜的步骤，使得金属镍膜覆盖绝缘膜和硅区域，形成第一硅化镍 在金属镍膜的硅区域的表面上主要由Ni 2 Si层构成，通过对硅衬底进行退火处理，除去金属镍膜，在形成第一 镍硅化物层，通过选择性湿蚀刻工艺，并且通过在硅烷气体中进行的热退火工艺将第一硅化镍层转化为主要由NiSi相的第二硅化镍层。

公开(公告)号：US07429525B2

公开(公告)日：2008-09-30

申请号：US11434202

申请日：2006-05-16

申请人： Yasunori Uchino ,  Kazuo Kawamura ,  Naoyoshi Tamura

发明人： Yasunori Uchino ,  Kazuo Kawamura ,  Naoyoshi Tamura

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/02068 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas ambient at a temperature not exceeding 220° C. to form a first nickel silicide layer having a composition primarily of Ni2Si on the silicon surface and a surface of the metallic nickel film, removing the metallic nickel film after the step of forming the nickel silicide layer by a wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of nickel monosilicide (NiSi) by applying a thermal annealing process.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在硅衬底上形成金属镍膜，使得金属镍膜覆盖硅衬底上的绝缘膜和硅衬底的硅表面，使硅衬底以硅烷 气体环境温度不超过220℃，以在硅表面上形成主要具有Ni 2 Si的组成的第一硅化镍层和金属镍膜的表面，除去金属镍 在通过湿式蚀刻工艺形成硅化镍层的步骤之后，通过进行热退火处理，将第一硅化镍层转化为主要由一氧化镍镍（NiSi）构成的第二硅化镍层。

公开(公告)号：US09214524B2

公开(公告)日：2015-12-15

申请号：US13586091

申请日：2012-08-15

申请人： Naoyoshi Tamura

发明人： Naoyoshi Tamura

IPC分类号： H01L21/8236 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/41783 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，嵌入到半导体衬底中的栅电极两侧的部分中的第一半导体层， 并且其包括Si和除Si之外的4B组元素，以及第二半导体层，其嵌入到半导体衬底中的栅电极的两侧的部分中，以便叠置在第一半导体层上，并且包括 Si和除Si以外的4B族元素，其中，所述栅电极比所述第二半导体层的端部与所述第一半导体层的端部分离。

公开(公告)号：US08741721B2

公开(公告)日：2014-06-03

申请号：US13109126

申请日：2011-05-17

申请人： Naoyoshi Tamura

发明人： Naoyoshi Tamura

IPC分类号： H01L21/31

CPC分类号： H01L21/823807 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

摘要翻译： 一种半导体器件及其制造方法，其能够使用廉价的结构来提高MOSFET的工作速度。 该方法包括以下步骤：形成应力膜以覆盖MOSFET的源极，漏极，侧壁绝缘层和栅极，并在应力膜中形成从应力膜表面向侧壁绝缘层延伸的狭缝。 结果，通过狭缝抑制了通过栅极上的应力膜中的局部应力分量使源极和漏极上的应力膜中的局部应力分量被松弛的效果。

公开(公告)号：US08740477B2

公开(公告)日：2014-06-03

申请号：US13386869

申请日：2010-07-27

申请人： Naoyoshi Tamura ,  Akihiro Shimotsu

发明人： Naoyoshi Tamura ,  Akihiro Shimotsu

IPC分类号： G02B6/36 ,  G02B6/42 ,  G02B6/38 ,  G02B6/00

CPC分类号： G02B6/36 ,  G02B6/3817 ,  G02B6/3897 ,  G02B6/4201 ,  G02B6/4214 ,  G02B6/4278 ,  G02B6/4292 ,  H01R12/592 ,  H01R12/83 ,  H01R12/85

摘要： A hybrid connector is disclosed. The hybrid connector comprises a cable, a plug and a connector housing. The cable has an optical waveguide and conductive wires disposed therein. The plug is connected to the cable. The connector housing is configured to mount on the plug. The connector housing is provided with a connector-side locking portion, an optical connection portion and an electrical connection portion.

摘要翻译： 公开了一种混合连接器。 混合连接器包括电缆，插头和连接器壳体。 电缆具有设置在其中的光波导和导线。 插头连接到电缆。 连接器壳体被配置成安装在插头上。 连接器壳体设置有连接器侧锁定部分，光学连接部分和电连接部分。

公开(公告)号：US08501571B2

公开(公告)日：2013-08-06

申请号：US13419713

申请日：2012-03-14

申请人： Naoyoshi Tamura

发明人： Naoyoshi Tamura

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/00 ,  H01L21/20 ,  H01L21/36 ,  H01L33/00 ,  H01L27/088

CPC分类号： H01L21/265 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.

摘要翻译： 半导体器件包括MOS晶体管，MOS晶体管上的源电极和漏电极，每个包括第一碳浓度的碳和第一磷浓度的磷和第二碳掺杂硅层的第一碳掺杂硅层， 第一碳化硅层，其包含比第一磷浓度高的第二磷浓度的磷，并且包括第二碳浓度小于或等于第一碳浓度的碳。

公开(公告)号：US08247283B2

公开(公告)日：2012-08-21

申请号：US13283312

申请日：2011-10-27

申请人： Naoyoshi Tamura

发明人： Naoyoshi Tamura

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/933

摘要： A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：（a）通过栅极绝缘膜在硅衬底上形成栅电极; （b）在硅衬底上形成具有不同蚀刻特性的绝缘膜和牺牲膜的叠层，覆盖栅电极，并各向异性地蚀刻层压，以在栅电极和栅极绝缘膜的侧壁上形成侧壁间隔物 ; （c）在侧壁间隔物的两侧将杂质注入到硅衬底中; （d）蚀刻硅衬底和牺牲膜以在硅衬底中形成凹陷，并且将每个侧壁衬垫的横截面形状改变为大致L形; （e）在凹槽中外延生长含Si-Ge的晶体; 和（f）沉积含有应力的绝缘膜，覆盖侧壁间隔物。