CROSS-LOGICAL ENTITY ACCELERATORS
    71.
    发明申请
    CROSS-LOGICAL ENTITY ACCELERATORS 有权
    跨逻辑实体加速器

    公开(公告)号:US20110107035A1

    公开(公告)日:2011-05-05

    申请号:US12610583

    申请日:2009-11-02

    IPC分类号: G06F12/08

    CPC分类号: G06F9/5077

    摘要: A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time.

    摘要翻译: 创建跨逻辑实体组,其包括要由多个逻辑实体共享的一个或多个加速器。 加速器上的实例是多个逻辑实体中通用的功能。 要实例化的功能例如在运行时动态地确定。

    Two-sided, dynamic cache injection control
    72.
    发明授权
    Two-sided, dynamic cache injection control 失效
    双面动态缓存注入控制

    公开(公告)号:US07865668B2

    公开(公告)日:2011-01-04

    申请号:US11958424

    申请日:2007-12-18

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0893

    摘要: A method, system, and computer program product for two-sided, dynamic cache injection control are provided. An I/O adapter generates an I/O transaction in response to receiving a request for the transaction. The transaction includes an ID field and a requested address. The adapter looks up the address in a cache translation table stored thereon, which includes mappings between addresses and corresponding address space identifiers (ASIDs). The adapter enters an ASID in the ID field when the requested address is present in the cache translation table. IDs corresponding to device identifiers, address ranges and pattern strings may also be entered. The adapter sends the transaction to one of an I/O hub and system chipset, which in turn, looks up the ASID in a table stored thereon and injects the requested address and corresponding data in a processor complex when the ASID is present in the table, indicating that the address space corresponding to the ASID is actively running on a processor in the complex. The ASIDs are dynamically determined and set in the adapter during execution of an application in the processor complex.

    摘要翻译: 提供了一种用于双面动态高速缓存注入控制的方法,系统和计算机程序产品。 I / O适配器生成I / O事务以响应接收到事务的请求。 交易包括一个ID字段和一个请求的地址。 适配器查找存储在其上的高速缓存转换表中的地址,其包括地址和对应的地址空间标识符(ASID)之间的映射。 当请求的地址存在于缓存转换表中时,适配器在ID字段中输入ASID。 还可以输入与设备标识符,地址范围和模式串相对应的ID。 适配器将事务发送到I / O集线器和系统芯片组之一,I / O集线器和系统芯片组依次在存储在其中的表中查找ASID,并且当ASID存在于表中时将所请求的地址和对应的数据注入处理器复杂 ,指示对应于ASID的地址空间正在复合体中的处理器上正在运行。 在处理器复合体中的应用程序执行期间,ASID在适配器中动态确定和设置。

    CACHE INJECTION USING CLUSTERING
    73.
    发明申请
    CACHE INJECTION USING CLUSTERING 有权
    使用聚类的缓存注入

    公开(公告)号:US20090157962A1

    公开(公告)日:2009-06-18

    申请号:US11958445

    申请日:2007-12-18

    IPC分类号: G06F12/08

    摘要: A method and system for cache injection using clustering are provided. The method includes receiving an input/output (I/O) transaction at an input/output device that includes a system chipset or input/output (I/O) hub. The I/O transaction includes an address. The method also includes looking up the address in a cache block indirection table. The cache block indirection table includes fields and entries for addresses and cluster identifiers (IDs). In response to a match resulting from the lookup, the method includes multicasting an injection operation to processor units identified by the cluster ID.

    摘要翻译: 提供了使用聚类进行高速缓存注入的方法和系统。 该方法包括在包括系统芯片组或输入/输出(I / O)集线器的输入/输出设备处接收输入/输出(I / O)事务。 I / O事务包括一个地址。 该方法还包括查找缓存块间接表中的地址。 缓存块间接表包括用于地址和簇标识符(ID)的字段和条目。 响应于从查找产生的匹配,该方法包括将注入操作多播到由集群ID标识的处理器单元。

    Multi-granular stream processing
    74.
    发明授权
    Multi-granular stream processing 有权
    多粒度流处理

    公开(公告)号:US08892762B2

    公开(公告)日:2014-11-18

    申请号:US12637972

    申请日:2009-12-15

    IPC分类号: G06F15/16 G06F9/50 H04L29/06

    CPC分类号: G06F9/5044 H04L65/605

    摘要: Stream processing is facilitated by distributing responsibility for processing the stream to multiple components of a computing environment. A programmable unit receives one or more streams and determines the operations to be performed for the one or more streams and which components of the computing environment are to perform those operations. It forwards data relating to the one or more streams to one or more components of the computing environment for processing and/or information purposes.

    摘要翻译: 通过将处理流的责任分配到计算环境的多个组件来促进流处理。 可编程单元接收一个或多个流并且确定要为一个或多个流执行的操作以及计算环境的哪些组件将执行这些操作。 它将与一个或多个流有关的数据转发到计算环境的一个或多个组件以用于处理和/或信息目的。

    SYSTEM TO PROVIDE COMPUTING SERVICES
    76.
    发明申请
    SYSTEM TO PROVIDE COMPUTING SERVICES 有权
    提供计算服务的系统

    公开(公告)号:US20120284730A1

    公开(公告)日:2012-11-08

    申请号:US13102622

    申请日:2011-05-06

    IPC分类号: G06F9/46

    CPC分类号: G06F9/5094 Y02D10/22

    摘要: A system is provided. The system includes a computing device by which first and second commands are inputted, first and second resources disposed in communication with the computing device to be receptive of the first command and responsive to the first command with first and second energy demands in first and second response times, respectively and a managing unit. The managing unit is disposed in communication with the computing device to be receptive of the first and second commands and with the first and second resources to allocate tasks associated with the first command to one of the first and second resources. The tasks are allocated in accordance with the second command and the second command is based on the first and second energy demands and the first and second response times.

    摘要翻译: 提供了一个系统。 该系统包括计算装置,通过该计算装置输入第一和第二命令,第一和第二资源被布置为与计算装置通信以接受第一命令,并响应第一命令,在第一和第二响应中具有第一和第二能量需求 分别和管理单位。 管理单元被布置为与计算设备通信以接受第一和第二命令,并且利用第一和第二资源将与第一命令相关联的任务分配给第一和第二资源之一。 任务根据第二命令分配,第二命令基于第一和第二能量需求以及第一和第二响应时间。

    ADAPTOR SYSTEM FOR AN ETHERNET NETWORK
    77.
    发明申请
    ADAPTOR SYSTEM FOR AN ETHERNET NETWORK 有权
    用于以太网的适配器系统

    公开(公告)号:US20120213507A1

    公开(公告)日:2012-08-23

    申请号:US13029536

    申请日:2011-02-17

    IPC分类号: H04B10/08

    摘要: An Ethernet adapter system may include a transmitter to insert a payload type identifier sequence in a generic frame procedure header to indicate that a network is a converged enhanced Ethernet network. The transmitter may insert idle sequences in a stream of data frames transmitted along a link. The system may include a receiver to recognize a condition and to force a loss of synchronization condition on the link that will be converted by the receiver into a loss of light condition. The receiver may scan the transmitted stream of data frames for invalid data frames and introduce a code into the stream of data frames whenever an invalid data frame is detected.

    摘要翻译: 以太网适配器系统可以包括发射机,以在通用帧过程报头中插入有效载荷类型标识符序列,以指示网络是融合增强型以太网。 发射机可以将空闲序列插入沿着链路传输的数据帧流中。 该系统可以包括用于识别条件并且迫使将由接收机转换成光损失的链路上的同步状态的丢失的接收机。 接收机可以扫描发送的无效数据帧的数据帧流,并且每当检测到无效数据帧时,将代码引入到数据帧流中。

    CONCURRENT EXECUTION OF REQUEST PROCESSING AND ANALYTICS OF REQUESTS
    78.
    发明申请
    CONCURRENT EXECUTION OF REQUEST PROCESSING AND ANALYTICS OF REQUESTS 有权
    请求处理和要求分析的同时执行

    公开(公告)号:US20110145366A1

    公开(公告)日:2011-06-16

    申请号:US12637951

    申请日:2009-12-15

    IPC分类号: G06F15/16

    CPC分类号: G06F9/52

    摘要: Request processing within a computing environment is facilitated. Request processing and analytics processing for the request are performed substantially concurrently in order to improve efficiency of request execution. The analytics processing is at least commenced, and may complete, prior to receiving an indication of success or failure of the request processing. If request processing fails, analytics processing ceases, if not already complete, and results of the analytic processing are not used.

    摘要翻译: 促进计算环境内的请求处理。 基本同时执行请求的请求处理和分析处理,以提高请求执行的效率。 在接收到请求处理的成功或失败的指示之前,分析处理至少开始并且可以完成。 如果请求处理失败,分析处理将停止,如果尚未完成,并且不使用分析处理的结果。

    Target computer processor unit (CPU) determination during cache injection using input/output I/O) hub/chipset resources
    79.
    发明授权
    Target computer processor unit (CPU) determination during cache injection using input/output I/O) hub/chipset resources 失效
    使用输入/输出I / O)集线器/芯片组资源在高速缓存注入期间的目标计算机处理器单元(CPU)确定

    公开(公告)号:US07958314B2

    公开(公告)日:2011-06-07

    申请号:US11958435

    申请日:2007-12-18

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0897 G06F12/0831

    摘要: A method, system, and computer program product for target computer processor unit (CPU) determination during cache injection using I/O hub/chipset resources are provided. The method includes creating a cache injection indirection table on the input/output (I/O) hub or chipset. The cache injection indirection table includes fields for address or address range, CPU identifier, and cache type. In response to receiving an input/output (I/O) transaction, the hub/chipset reads the address in an address field of the I/O transaction, looks up the address in the cache injection indirection table, and injects the address and data of the I/O transaction to a target cache associated with a CPU as identified in the CPU identifier field when, in response to the look up, the address is present in the address field of the cache injection indirection table.

    摘要翻译: 提供了使用I / O集线器/芯片组资源的高速缓存注入期间的目标计算机处理器单元(CPU)确定的方法,系统和计算机程序产品。 该方法包括在输入/输出(I / O)集线器或芯片组上创建高速缓存注入间接表。 高速缓存注入间接表包括用于地址或地址范围,CPU标识符和缓存类型的字段。 响应于接收到输入/输出(I / O)事务,集线器/芯片组读取I / O事务的地址字段中的地址,查找缓存注入间接表中的地址,并注入地址和数据 的I / O事务发送到与CPU标识符字段中所标识的CPU相关联的目标缓存器,当响应于查找时,地址存在于高速缓存注入间接表的地址字段中。

    MANAGING TASK EXECUTION ON ACCELERATORS
    80.
    发明申请
    MANAGING TASK EXECUTION ON ACCELERATORS 失效
    管理加速器上的任务执行

    公开(公告)号:US20110131580A1

    公开(公告)日:2011-06-02

    申请号:US12627055

    申请日:2009-11-30

    IPC分类号: G06F9/46

    摘要: Execution of tasks on accelerator units is managed. The managing includes multi-level grouping of tasks into groups based on defined criteria, including start time of tasks and/or deadline of tasks. The task groups and possibly individual tasks are mapped to accelerator units to be executed. During execution, redistribution of a task group and/or an individual task may occur to optimize a defined energy profile.

    摘要翻译: 对加速器单元上的任务进行管理。 管理包括基于定义的标准将任务多层次分组成组,包括任务的开始时间和/或任务的最后期限。 任务组和可能的单个任务被映射到要执行的加速器单元。 在执行期间,可能发生任务组和/或单个任务的重新分配以优化所定义的能量分布。