公开(公告)号：US06847562B2

公开(公告)日：2005-01-25

申请号：US10185247

申请日：2002-06-28

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C11/39 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C16/04

CPC分类号： G11C11/39 ,  G11C11/413

摘要： An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

摘要翻译： 公开了一种增强的写入和读取存储器件的方法，例如使用负差分电阻（NDR）元件的SRAM）。 这通过选择性地控制存储器单元中的有源元件的偏置来完成。 例如在写入操作中，存储单元被置于中间状态以增加写入速度。 在基于NDR的实施例中，这是通过减小NDR FET的偏置电压来完成的，以便在写入操作期间削弱NDR元件（从而禁用NDR效应）。 相反，在读取操作期间，偏置电压增加以增加峰值电流（以及NDR效应），并且因此向BIT线提供额外的电流驱动。 使用这种程序的实施例实现了优异的峰谷电流比（PVR），读/写速度等。

公开(公告)号：US06795337B2

公开(公告)日：2004-09-21

申请号：US10185568

申请日：2002-06-28

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C1100

CPC分类号： G11C11/412 ,  G11C2211/5614

摘要： A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.

摘要翻译： 公开了一种双端子硅基负差动电阻（NDR）元件，以实现用于所选应用的一种NDR二极管。 两端子器件基于具有修改的沟道掺杂分布的三端NDR功能FET，其中栅极连接到漏极。 该器件可以通过常规CMOS处理与其他NDR和非NDR元件（包括具有NDR功能的FET）进行集成。 还公开了使用这种NDR两端元件和NDR三端的存储单元。

公开(公告)号：US06754104B2

公开(公告)日：2004-06-22

申请号：US10028084

申请日：2001-12-21

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C1604

CPC分类号： G11C5/142 ,  B82Y10/00 ,  G11C11/39 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device including integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.

摘要翻译： 包括集成绝缘栅场效应晶体管（IGFET）元件和一个或多个负差分电阻（NDR）场效应晶体管元件的半导体器件，其组合并形成在公共基板上。 因此，包括逻辑和存储器在内的各种电路通过常规和具有NDR功能的FET的组合来实现。 因为这两种类型的元件共享许多共同特征，所以它们可以用通常的加工操作来制造，以便在制造设备中实现更好的集成。

公开(公告)号：US06724655B2

公开(公告)日：2004-04-20

申请号：US10029077

申请日：2001-12-21

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C1100

CPC分类号： G11C5/142 ,  B82Y10/00 ,  G11C11/39 ,  G11C11/41 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

摘要： A memory cell using both negative differential resistance (NDR) and conventional FETs is disclosed. A pair of NDR FETs are coupled in a latch configuration so that a data value passed by a transfer FET can be stored at a storage node. By exploiting an NDR characteristic, the memory cell can be implemented with fewer active devices. Moreover, an NDR FET can be manufactured using conventional MOS processing steps so that process integration issues are minimized as compared to conventional NDR techniques.

摘要翻译： 公开了使用负差分电阻（NDR）和常规FET的存储单元。 一对NDR FET以锁存配置耦合，使得由传输FET传递的数据值可以存储在存储节点处。 通过利用NDR特性，可以使用较少的活动设备实现存储器单元。 此外，可以使用常规MOS处理步骤来制造NDR FET，使得与常规NDR技术相比，处理集成问题被最小化。

公开(公告)号：US06693027B1

公开(公告)日：2004-02-17

申请号：US10298917

申请日：2002-11-18

申请人： Tsu-Jae King ,  David K. Y. Liu

发明人： Tsu-Jae King ,  David K. Y. Liu

IPC分类号： H01L2128

CPC分类号： H01L29/7881 ,  G11C5/142 ,  H01L29/788 ,  H01L29/792

摘要： A process for forming/configuring a device to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is implemented by incorporating a dynamic threshold voltage in such device. An onset point for the NDR characteristic is also adjustable during a manufacturing process to enhance the performance of an NDR device.

摘要翻译： 公开了一种用于形成/配置器件以包括负差分电阻（NDR）特性的过程。 在FET实施例中，通过在该装置中并入动态阈值电压来实现NDR特性。 在制造过程中，NDR特性的起始点也是可调节的，以增强NDR设备的性能。

公开(公告)号：US06686267B1

公开(公告)日：2004-02-03

申请号：US10298915

申请日：2002-11-18

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L2128

CPC分类号： B82Y10/00 ,  G11C5/142 ,  G11C11/39 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/905

摘要： A process for forming a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is selectively enabled/disabled by forming a body contact bias, thus permitting a dual behavior of the device. Larger collections of such FETs can be synthesized to form dual mode logic circuits as well, so that a single circuit can perform more than one logic operation depending on whether an NDR mode is enabled or not.

摘要翻译： 公开了一种用于形成双模式FET的过程和包括负差分电阻（NDR）特性的逻辑电路。 在FET实施例中，通过形成身体接触偏压来选择性地启用/禁用NDR特性，从而允许器件的双重行为。 可以合成更大的这种FET的集合以形成双模逻辑电路，使得单个电路可以执行多于一个的逻辑操作，这取决于是否启用NDR模式。

公开(公告)号：US06680245B1

公开(公告)日：2004-01-20

申请号：US10232129

申请日：2002-08-30

申请人： Tsu-Jae King ,  David K. Y. Liu

发明人： Tsu-Jae King ,  David K. Y. Liu

IPC分类号： H01L2128

CPC分类号： H01L29/7881 ,  G11C5/142 ,  H01L29/788 ,  H01L29/792

摘要： A semiconductor manufacturing process is disclosed that is suitable for making both negative differential resistance (NDR) and non-NDR devices at the same time. An NDR process is thus integrated within a conventional CMOS process so that compatibility with existing fabrication procedures is maintained. In addition, many of the NDR process steps and non-NDR process steps are shared in common to form features of such devices at the same time.

摘要翻译： 公开了适用于同时制造负差分电阻（NDR）和非NDR器件的半导体制造工艺。 因此，NDR工艺集成在常规CMOS工艺中，以便保持与现有制造工艺的兼容性。 此外，许多NDR流程步骤和非NDR流程步骤共同共享，以同时形成这些设备的功能。

公开(公告)号：US06567292B1

公开(公告)日：2003-05-20

申请号：US10185569

申请日：2002-06-28

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C506

CPC分类号： G11C5/005 ,  G11C11/4125

摘要： An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

摘要翻译： 公开了一种使用这种元件的有源负差分电阻元件（NDR FET）和存储器件（例如SRAM）。 NDR FET和这种存储器件的软错误率（SER）性能通过调整负责实现NDR行为的电荷陷阱层中的电荷陷阱的位置来增强。 SER和开关速度性能特性都可以通过充电陷阱的适当放置来定制。

公开(公告)号：US06210988B1

公开(公告)日：2001-04-03

申请号：US09483222

申请日：2000-01-14

申请人： Roger T. Howe ,  Andrea Franke ,  Tsu-Jae King

发明人： Roger T. Howe ,  Andrea Franke ,  Tsu-Jae King

IPC分类号： H01L2100

CPC分类号： B81C1/00246 ,  B81B2203/0118 ,  B81C2201/0109 ,  B81C2203/0735 ,  Y10S438/933

摘要： This invention relates to micro-electromechanical systems using silicon-germanium films.

摘要翻译： 本发明涉及使用硅 - 锗膜的微机电系统

公开(公告)号：US5401982A

公开(公告)日：1995-03-28

申请号：US205974

申请日：1994-03-03

申请人： Tsu-Jae King ,  Michael G. Hack

发明人： Tsu-Jae King ,  Michael G. Hack

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/786 ,  H01L29/78

CPC分类号： H01L29/78696 ,  H01L29/66757 ,  H01L29/78609 ,  H01L29/78621 ,  H01L2029/7863

摘要： In the channel layer of a thin film transistor (TFT), a channel and its drain meet at a transition within a transition region. The channel extends in a first, or horizontal, dimension away from the drain and extends in a second, or vertical, dimension from a side away from the gate to a side toward the gate. The charge carrier densities in the transition region vary in the second dimension in a way that reduces leakage current, because the position of the maximum electric field is moved away from the gate and its magnitude is reduced. Variation of densities in the second dimension can be produced by high angle implantation of a dopant and a counterdopant, providing a transition region between the drain and the channel underneath the gate. Variation of densities in the second dimension can also be produced with non-angled implantation by a process in which a sidewall spacer offsets the drain, providing a transition region that is between the drain and the channel and that can be doped independently of the drain. In a symmetric TFT in which either channel lead can function as a drain, charge carrier densities can vary in the second dimension at the transitions between each channel lead and the channel.

摘要翻译： 在薄膜晶体管（TFT）的沟道层中，沟道及其漏极在过渡区域内的过渡处相遇。 该通道在远离排水口的第一或水平尺寸上延伸，并且从第二或垂直尺寸的一侧向远离浇口的一侧延伸到一侧朝向浇口。 过渡区域中的电荷载流子密度在第二维度上以减少泄漏电流的方式变化，因为最大电场的位置移动离开栅极并且其幅度减小。 可以通过掺杂剂和反掺杂剂的高角度注入来产生第二维度中的密度变化，从而在栅极下方的漏极和沟道之间提供过渡区域。 第二维度中的密度的变化也可以通过其中侧壁间隔件抵消漏极的过程以非倾斜注入产生，提供位于漏极和沟道之间的过渡区域，并且可以独立于漏极掺杂。 在其中任一通道引线可用作漏极的对称TFT中，电荷载流子密度可以在每个通道引线和通道之间的转换处在第二维度上变化。