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    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY
    71.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY 有权

    公开(公告)号：US20210167201A1

    公开(公告)日：2021-06-03

    申请号：US17176146

    申请日：2021-02-15

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach

    IPC: H01L29/78 ,  H01L27/11 ,  H01L27/11578 ,  G11C16/02 ,  G11C11/404 ,  H01L27/24 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/115 ,  G11C16/04 ,  G11C11/412

    Abstract: A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

    3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS
    75.
    发明申请
    3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS 有权

    公开(公告)号：US20210151450A1

    公开(公告)日：2021-05-20

    申请号：US16649660

    申请日：2018-09-23

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

    IPC: H01L27/11556 ,  H01L23/66 ,  H01L23/538 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

    Abstract: A 3D device, the device including: at least a first level including logic circuits; at least a second level including an array of memory cells; at least a third level including special circuits; and at least a fourth level including special connectivity structures, where the special connectivity structures include one of the following: a. waveguides, or b. differential signaling, or c. radio frequency transmission lines, or d. Surface Waves Interconnect (SWI) lines, and where the third level includes Radio Frequency (“RF”) circuits to drive the special connectivity structures, where the second level overlays the first level, where the third level overlays the second level, and where the fourth level overlays the third level.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE
    76.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE 有权

    公开(公告)号：US20210143217A1

    公开(公告)日：2021-05-13

    申请号：US17121741

    申请日：2020-12-14

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

    IPC: H01L27/24 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/12 ,  H01L29/78 ,  H01L29/423 ,  H01L27/22

    Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer, a first metal layer, a second metal layer above the first metal layer, and a third metal layer above the second metal layer, where the second metal layer is significantly thicker than either the third metal layer or the first metal layer, where the third metal layer is precisely aligned to the first metal layer with less than 20 nm misalignment; a second level including a first array of first memory cells, each of the first memory cells include first transistors; a third level including a second array of second memory cells, each of the second memory cells include second transistors, where the second level is above the third level, where the second transistors are self-aligned to the first transistors, being processed following the same lithography step; and periphery circuits connected by the second metal to control the memory cells, where the periphery circuits are either underneath or atop the memory cells.

    3D semiconductor device and structure
    78.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US11004694B1

    公开(公告)日：2021-05-11

    申请号：US17115766

    申请日：2020-12-08

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/098 ,  H01L23/522 ,  H01L23/367 ,  H01L27/092 ,  H01L25/00 ,  H01L23/60 ,  H01L25/065 ,  H01L23/373

    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, and where the third layer includes material other than silicon.

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