公开(公告)号：US07050318B1

公开(公告)日：2006-05-23

申请号：US10957060

申请日：2004-10-01

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/00 ,  G11C7/00

CPC classification number: G11C15/00 ,  G11C7/12 ,  G11C15/04

Abstract: A CAM device for comparing a search key with a plurality of CAM words stored in a main CAM array includes a pre-compare CAM array and match line control logic. The pre-compare CAM array includes a plurality of rows, each for storing a set of pre-compare bits generated by performing a logical function on a corresponding CAM word. The match line control logic selectively pre-charges match lines in the main CAM array in response to match results from a pre-compare operation between an encoded search key and corresponding sets of pre-compare bits.

Abstract translation: 用于将搜索关键字与存储在主CAM阵列中的多个CAM字进行比较的CAM装置包括预比较CAM阵列和匹配线控制逻辑。 预比较CAM阵列包括多行，每行用于存储通过在对应的CAM字执行逻辑功能而生成的一组预比较位。 匹配线控制逻辑有选择地预先对主CAM阵列中的匹配线进行预充电，以响应来自编码的搜索关键字和对应的预比较比特组之间的预比较操作的匹配结果。

公开(公告)号：US06967855B2

公开(公告)日：2005-11-22

申请号：US10639153

申请日：2003-08-11

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna

IPC: G11C15/04 ,  G06F17/30 ,  G11C15/00 ,  H04L12/56

CPC classification number: G06F17/30982 ,  G11C15/00

Abstract: A method and apparatus are described for the filtering of a common input string to generate various filtered comparand strings. The filtering of a common input string enables concurrent lookups in different tables to be performed on multiple filtered comparands by different CAM devices (or different blocks within a CAM device), to compare the data in the filtered comparand strings with data stored in its associative memory. By performing multiple lookups in parallel, rather than sequentially, packet throughput in a CAM may be significantly increased.

Abstract translation: 描述了用于过滤公共输入串以产生各种经过滤的比较串的方法和装置。 公共输入字符串的过滤使得可以通过不同的CAM设备（或CAM设备内的不同块）在多个经滤波的比较上对不同表格中的并发查找进行比较，以将滤波后的比较串中的数据与存储在其关联存储器中的数据进行比较 。 通过并行执行多个查找，而不是依次执行CAM中的数据包吞吐量可能会显着增加。

公开(公告)号：US06914795B1

公开(公告)日：2005-07-05

申请号：US10734666

申请日：2003-12-12

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna

IPC: G11C15/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is couple to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.

Abstract translation: 具有选择性错误记录的内容可寻址存储器（CAM）设备。 CAM设备包括CAM阵列和错误检测电路，该电路被耦合以从CAM阵列内的所选择的存储位置接收数据值，该错误检测电路适于根据数据值是否包括错误来产生错误指示。 错误存储电路耦合以从错误检测电路接收错误指示，并且适于存储对应于所选存储位置的错误地址，如果错误指示指示数据值包括错误，并且如果错误地址不是 已经存储在错误存储电路中。

公开(公告)号：US06906937B1

公开(公告)日：2005-06-14

申请号：US10394983

申请日：2003-03-21

Applicant: Bindiganavale S. Nataraj

Inventor： Bindiganavale S. Nataraj

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM). Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line control circuit includes a dynamic component and a static component to control the bit line.

Abstract translation: 位线控制电路耦合在相关联的内容可寻址存储器（CAM）的位线之间。 阵列和电源电压。 位线控制电路响应于位线控制信号调整位线的充电电流。 对于一些实施例，位线控制电路包括用于控制位线的动态分量和静态分量。

公开(公告)号：US06865098B1

公开(公告)日：2005-03-08

申请号：US10449422

申请日：2003-05-30

Applicant: Michael Edwin Ichiriu ,  Masaru Shinohara ,  YueFei Ge ,  Lan Lee

Inventor： Michael Edwin Ichiriu ,  Masaru Shinohara ,  YueFei Ge ,  Lan Lee

IPC: G11C15/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.

Abstract translation: 内容寻址存储器（CAM）具有包括多个CAM单元行的主阵列，可选择的一个或多个备用行CAM单元，用于功能地替代主阵列中的CAM单元的有缺陷的行，以及用于禁用故障的控制电路 将预定数据写入CAM单元的有缺陷的行。

公开(公告)号：US06864122B1

公开(公告)日：2005-03-08

申请号：US10321160

申请日：2002-12-17

Applicant: Charles C. Huse ,  William G. Nurge ,  Varadarajan Srinivasan

Inventor： Charles C. Huse ,  William G. Nurge ,  Varadarajan Srinivasan

IPC: G11C5/00 ,  G11C15/00 ,  H01L23/50 ,  H01L25/065 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/50 ,  G11C15/00 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A monolithic Multi-chip Module (MCM) package includes two or more individual CAM dice mounted on a substrate formed as, for example, a plastic ball grid array (PBGA) package. The substrate includes an interconnect structure to route signals between corresponding pads of the CAM dice and balls of the MCM package. In some embodiments, the footprint of the MCM ball grid array package is identical to the footprint of a similar PBGA package housing a single CAM die. Each CAM die within the MCM package may be assigned the same device identification number (DID).

Abstract translation: 单片多芯片模块（MCM）封装包括安装在例如塑料球栅阵列（PBGA）封装形成的基板上的两个或多个单独的CAM裸片。 衬底包括互连结构，用于在CAM芯片的相应焊盘和MCM封装的球之间路由信号。 在一些实施例中，MCM球栅阵列封装的封装与容纳单个CAM裸片的类似PBGA封装的封装相同。 MCM封装中的每个CAM裸片可以分配相同的器件标识号（DID）。

公开(公告)号：US06845026B1

公开(公告)日：2005-01-18

申请号：US10452216

申请日：2003-05-30

Applicant: Nilesh A. Gharia

Inventor： Nilesh A. Gharia

IPC: G11C15/04 ,  G11C15/00 ,  G06F12/00 ,  G11C7/00 ,  G11C11/00 ,  G11C11/34

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) cell includes a memory cell storing data values. The memory cell includes a surrounding-gate thyristor and an access transistor. The CAM cell also includes a compare circuit coupled among the memory cell and a match line. The compare circuit receives data and comparand data and affects a logical state of a match line in response to a predetermined relationship between the data and comparand data. The compare circuit includes a first transistor set coupled for conduction state control by signals representative of the data, and a second transistor set coupled for conduction state control by signals representative of the comparand data.

Abstract translation: 内容可寻址存储器（CAM）单元包括存储数据值的存储单元。 存储单元包括周围栅极晶闸管和存取晶体管。 CAM单元还包括耦合在存储单元和匹配线之间的比较电路。 比较电路接收数据和比较数据，并且响应于数据和比较数据之间的预定关系影响匹配线的逻辑状态。 比较电路包括通过表示数据的信号耦合用于导通状态控制的第一晶体管组，以及通过表示比较数据的信号耦合用于导通状态控制的第二晶体管组。

公开(公告)号：US6154384A

公开(公告)日：2000-11-28

申请号：US439317

申请日：1999-11-12

Applicant: Bindiganavale S. Nataraj ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Bindiganavale S. Nataraj ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory (CAM) cell. For one embodiment, the ternary CAM cell includes a first memory cell, a compare circuit, a second memory cell and a mask circuit. The first memory cell is coupled to a first pair of bit lines that carries data to and from the first memory cell. The compare circuit receives comparand data on a pair of compare signal lines, and compares the comparand data with the data stored in the first memory cell. The compare circuit includes a pair of transistors and a match transistor. The pair of transistors receives the comparand data on the compare signal lines and also receives the data stored in the first memory cell. The match transistor determines the state of a match line. The second memory cell stores mask data that may mask the comparison result such that it does not affect the logical state of the match line.

Abstract translation: 三元内容可寻址存储器（CAM）单元。 对于一个实施例，三元CAM单元包括第一存储单元，比较电路，第二存储单元和掩模电路。 第一存储器单元耦合到第一对位线，其将数据传送到第一存储器单元并从第一存储单元传送数据。 比较电路在一对比较信号线上接收比较数据，并将比较数据与存储在第一存储单元中的数据进行比较。 比较电路包括一对晶体管和匹配晶体管。 该对晶体管在比较信号线上接收比较数据，并且还接收存储在第一存储单元中的数据。 匹配晶体管确定匹配线的状态。 第二存储器单元存储可以掩蔽比较结果使得其不影响匹配线的逻辑状态的掩码数据。

公开(公告)号：US6148364A

公开(公告)日：2000-11-14

申请号：US001110

申请日：1997-12-30

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00 ,  G11C15/04 ,  G06F12/02

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A method and apparatus for cascading content addressable memory (CAM) devices is disclosed. The method and apparatus may be particularly useful when depth cascading CAM devices that operate in a flow-through mode. In the flow-through mode, a compare instruction may be simultaneously provided to each CAM device in the cascade, and the match address, data stored at the matched location, or other status information may then be output to a common output data bus by the highest priority matching CAM device in the same cycle that the instruction is provided to the CAM devices. Each CAM device may have a cascade input and a cascade output to perform the cascade function. The cascade output of a higher priority CAM device may be connected to the cascade input of the next lower priority CAM device. The higher priority CAM device may assert a cascade signal on its cascade output at a predetermined time after receiving an input signal (e.g., a clock signal). Asserting the cascade signal may indicate that the higher priority CAM device has completed the compare instruction. When the lower priority CAM device detects that the cascade signal has been asserted on its cascade input, the lower priority CAM device may sample the match flag of the higher priority CAM device to determine if the lower priority CAM device may output its data to the common output data bus.

Abstract translation: 公开了用于级联内容可寻址存储器（CAM）设备的方法和装置。 当以流通模式操作的深度级联CAM设备时，该方法和设备可能是特别有用的。 在流通模式中，可以在级联中同时向每个CAM设备提供比较指令，并且匹配地址，存储在匹配位置的数据或其他状态信息然后可以被输出到公共输出数据总线 在CAM指令提供给CAM设备的同一周期内，最高优先级的匹配CAM设备。 每个CAM设备可以具有级联输入和级联输出以执行级联功能。 较高优先级的CAM设备的级联输出可以连接到下一个较低优先级的CAM设备的级联输入。 较高优先级的CAM设备可以在接收到输入信号（例如，时钟信号）之后的预定时间在其级联输出上断言级联信号。 断开级联信号可能表明较高优先级的CAM设备已经完成了比较指令。 当较低优先级的CAM设备检测到级联信号已经在其级联输入上被断言时，较低优先级的CAM设备可以对较高优先级的CAM设备的匹配标志进行采样，以确定较低优先级的CAM设备是否可以将其数据输出到公共 输出数据总线。

公开(公告)号：US06125049A

公开(公告)日：2000-09-26

申请号：US225919

申请日：1999-01-05

Applicant: Bindiganavale S. Nataraj

Inventor： Bindiganavale S. Nataraj

IPC: G06F7/02 ,  G11C15/04 ,  G11C15/00

CPC classification number: G06F7/02 ,  G11C15/04

Abstract: A match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pull-up transistor coupled between a match line of an associated CAM and a supply voltage. Prior to compare operations, both the static pull-up transistor and the dynamic pull-up transistor are in a conductive state and thereby quickly charge the match line to the supply voltage. During compare operations, the dynamic transistor is turned off to reduce current flow between the supply voltage and the match line. In some embodiments, the static pull-up transistor and the dynamic pull-up transistor are configured to match the parasitics of the CAM cells 10 coupled to the match line, thereby increasing performance of the associated CAM.