公开(公告)号：US20050199939A1

公开(公告)日：2005-09-15

申请号：US10799060

申请日：2004-03-12

申请人： Jeffrey Lutze ,  Tuan Pham ,  Masaaki Higashitani

发明人： Jeffrey Lutze ,  Tuan Pham ,  Masaaki Higashitani

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521

摘要： A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. A first process forms floating gates by etching an upper portion of a polysilicon structure with masking elements in place to shape the floating gate. A second process etches recesses and protrusions in a polysilicon structure prior to etching the structure to form individual floating gates.

摘要翻译： 非易失性存储器阵列具有耦合到浮动栅极的字线，浮动栅极具有适于提供增加的表面积的上部部分，从而提供增加的与字线的耦合。 还提供了浮动门之间的屏蔽。 第一工艺通过用掩蔽元件蚀刻多晶硅结构的上部来形成浮栅来形成浮栅，以形成浮栅。 在蚀刻结构之前，第二工艺蚀刻多晶硅结构中的凹陷和突起以形成单独的浮动栅极。

公开(公告)号：US06492695B2

公开(公告)日：2002-12-10

申请号：US09250590

申请日：1999-02-16

申请人： Jeffrey Lutze

发明人： Jeffrey Lutze

IPC分类号： H01L2976

CPC分类号： H01L29/512 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518

摘要： According to one example embodiment, the present invention is directed to a semiconductor device, wherein the device includes a transistor having source and drain regions separated by a channel region. The device includes a gate formed over the channel region and formed over part of the source region and over part of the drain region. The device further includes an insulator region configured and arranged to insulate the gate from the channel region and from the source and drain regions. The insulator region has a first material arranged over the channel region and providing a high dielectric constant, and has a second material arranged over part of the source region and over part of the drain region and providing a significantly lower dielectric constant. By using insulator materials having different dielectric constants, this embodiment not only meets the compact size requirements of higher-functioning devices, but also adequately insulates the gate and channel regions and improves the transistor performance.

摘要翻译： 根据一个示例实施例，本发明涉及一种半导体器件，其中该器件包括具有由沟道区分隔开的源极和漏极区域的晶体管。 该器件包括形成在沟道区上并形成在源极区的一部分上方以及漏极区的一部分上的栅极。 该器件还包括被配置和布置成使栅极与沟道区域以及源极和漏极区域绝缘的绝缘体区域。 绝缘体区域具有布置在沟道区域上并提供高介电常数的第一材料，并且具有布置在源极区域的一部分和漏极区域的一部分上并提供显着较低介电常数的第二材料。 通过使用具有不同介电常数的绝缘体材料，该实施例不仅满足较高功能器件的紧凑尺寸要求，而且还使栅极和沟道区域充分绝缘并提高晶体管性能。

公开(公告)号：US06262455B1

公开(公告)日：2001-07-17

申请号：US09431841

申请日：1999-11-02

申请人： Jeffrey Lutze ,  Emmanuel de Muizon

发明人： Jeffrey Lutze ,  Emmanuel de Muizon

IPC分类号： H01L2972

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： A method for manufacturing a semiconductor device that includes dual gate oxide layers made of two dielectric layers of varying thickness on a single wafer. In an example embodiment, a semiconductor structure is fabricated by providing a first layer of a dielectric over a semiconductor material and covering the first layer with a protective second dielectric layer adapted to mask the first layer. The first and second layers are then removed over a region of the semiconductor material while the second layer is used to protect the first layer, therein leaving the region of semiconductor material substantially exposed. A third layer of dielectric material is formed over the first and second layers and the adjacent exposed semiconductor material region; a gate material is then formed over the third dielectric layer. Finally, an etching step etches through the gate material and underlying layers to the semiconductor material to form a thick gate region and a thin gate region. The thick and thin gate regions can be formed on the same substrate using substantially the same manufacturing process.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括由单个晶片上具有不同厚度的两个电介质层制成的双栅极氧化物层。 在示例性实施例中，通过在半导体材料上提供电介质的第一层并且用适于掩蔽第一层的保护性第二介电层覆盖第一层来制造半导体结构。 然后在半导体材料的区域上去除第一层和第二层，而第二层用于保护第一层，其中使半导体材料的区域基本上暴露。 在第一和第二层和相邻的暴露的半导体材料区域上形成第三层电介质材料; 然后在第三电介质层上形成栅极材料。 最后，蚀刻步骤通过栅极材料和下面的层蚀刻到半导体材料以形成厚栅区和薄栅区。 可以使用基本上相同的制造工艺在同一基板上形成厚且薄的栅极区域。

公开(公告)号：US5736435A

公开(公告)日：1998-04-07

申请号：US497317

申请日：1995-07-03

申请人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze ,  Sergio Ajuria

发明人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze ,  Sergio Ajuria

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L29/786 ,  H01L21/00 ,  H01L21/3205

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L29/78618 ,  H01L29/78648

摘要： A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).

摘要翻译： 在SOI衬底上制造MOSFET的工艺包括形成由场隔离区域（16,18）和绝缘层（12）隔离的有源区域（14）。 使用其中具有开口（24）的掩模层（22）在有源区域（14）中形成凹部（26）。 在凹部（26）中形成栅介电层（32），沉积多晶硅层（34）以覆盖掩模层（22）并填充凹部（26）。 进行平面化处理以在凹部（26）中形成栅电极（36），并且源极和漏极区域（40,42）以与栅电极（36）自对准的方式形成。 通道区域（44）位于源极和漏极区域（40,42）的中间，并且位于栅电极（36）的正下方。