Method of forming capacitors
    81.
    发明授权
    Method of forming capacitors 有权
    形成电容器的方法

    公开(公告)号:US08088659B2

    公开(公告)日:2012-01-03

    申请号:US12769306

    申请日:2010-04-28

    IPC分类号: H01L21/8242

    摘要: High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.

    摘要翻译: 通过相应氮化物的顺序化学气相沉积(CVD)形成钛和钨或钛和钽的混合过渡金属氧化物的高介电膜,并在氧的存在下退火以致密化和氧化氮化物。 所得到的膜可用作电容性电池并且抵抗向下层材料的氧扩散,具有高电容和低电流泄漏。

    Capacitor formed on a recrystallized polysilicon layer
    82.
    发明授权
    Capacitor formed on a recrystallized polysilicon layer 有权
    在再结晶的多晶硅层上形成的电容器

    公开(公告)号:US08053296B2

    公开(公告)日:2011-11-08

    申请号:US12478512

    申请日:2009-06-04

    IPC分类号: H01L21/00

    CPC分类号: H01L28/40 H01L27/1085

    摘要: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.

    摘要翻译: 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 除了其他元件之外,半导体器件包括位于栅电极层143上的再结晶多晶硅层148,位于再结晶多晶硅层148上的电容器170.在该实施例中,电容器170包括第一电极173,绝缘体175 位于第一电极173上方,以及位于绝缘体175上方的第二电极178。

    FUSI integration method using SOG as a sacrificial planarization layer
    84.
    发明授权
    FUSI integration method using SOG as a sacrificial planarization layer 有权
    使用SOG作为牺牲平坦化层的FUSI积分方法

    公开(公告)号:US07943499B2

    公开(公告)日:2011-05-17

    申请号:US12603169

    申请日:2009-10-21

    IPC分类号: H01L21/28 H01L21/44

    摘要: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

    摘要翻译: 一种制造晶体管20的方法,其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露 在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。 如果使用过渡金属氮化物层200,则在栅电极90完全硅化之前,从栅电极93的顶部去除它。

    CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER
    86.
    发明申请
    CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER 有权
    电容器在重组多晶硅层上形成

    公开(公告)号:US20100159665A1

    公开(公告)日:2010-06-24

    申请号:US12478512

    申请日:2009-06-04

    IPC分类号: H01L21/02

    CPC分类号: H01L28/40 H01L27/1085

    摘要: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.

    摘要翻译: 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 除了其他元件之外,半导体器件包括位于栅电极层143上的再结晶多晶硅层148,位于再结晶多晶硅层148上的电容器170.在该实施例中,电容器170包括第一电极173,绝缘体175 位于第一电极173上方,以及位于绝缘体175上方的第二电极178。

    FUSI Integration Method Using SOG as a Sacrificial Planarization Layer
    88.
    发明申请
    FUSI Integration Method Using SOG as a Sacrificial Planarization Layer 有权
    使用SOG作为牺牲平面化层的FUSI集成方法

    公开(公告)号:US20100041231A1

    公开(公告)日:2010-02-18

    申请号:US12603169

    申请日:2009-10-21

    IPC分类号: H01L21/30

    摘要: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

    摘要翻译: 一种制造晶体管20的方法,其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露 在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。 如果使用过渡金属氮化物层200,则在栅电极90完全硅化之前,从栅电极93的顶部去除。

    Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device
    89.
    发明授权
    Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device 有权
    用独立的栅极和源极/漏极掺杂形成完全硅化半导体器件的方法及相关器件

    公开(公告)号:US07585738B2

    公开(公告)日:2009-09-08

    申请号:US11741540

    申请日:2007-04-27

    IPC分类号: H01L21/336 H01L21/44

    摘要: A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

    摘要翻译: 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法(包括多晶硅层和阻挡层的栅极堆叠),以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入)。