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公开(公告)号：US12004374B2
公开(公告)日：2024-06-04
申请号：US17438999
申请日：2021-07-26
Inventor： Chuanbao Luo
IPC: H01L21/00 , G02F1/1362 , G02F1/1368 , H10K59/12 , H10K59/121 , H10K59/65
CPC classification number: H10K59/1213 , G02F1/136209 , G02F1/1368 , H10K59/1201 , H10K59/65
Abstract: A display panel, a manufacturing method thereof, and a display device are provided. Through a configuration of a capacitor in the display panel, where the capacitor is connected to a first thin film transistor, a photosensitive pattern in the capacitor senses light, such that when the light varies, a varying charge quantity of the photosensitive pattern in the capacitor varies current of the first thin film transistor, increasing a sensitometric characteristic of the first thin film transistor, and increasing fingerprint recognition effect, and a second gate is configured to be a capacitor polar plate, decreasing a thickness of an array substrate.
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公开(公告)号：US12002403B1
公开(公告)日：2024-06-04
申请号：US18309813
申请日：2023-04-30
Inventor： Jhenwei He
IPC: G09G3/20
CPC classification number: G09G3/2074 , G09G2300/0452 , G09G2300/0465 , G09G2320/0233 , G09G2320/0242 , G09G2320/08
Abstract: A pixel arrangement structure and a display panel are provided by the present disclosure. The pixel arrangement structure includes at least one pixel group, and the pixel group includes a plurality of sub-pixels arranged in an array. In the pixel group, a ratio of a number of high-grayscale subpixels to a number of low-grayscale subpixels is 1:2 or 1:3. The low-grayscale subpixels include a plurality of first low-grayscale subpixels, and among adjacent N rows of the subpixels, the number of the high-grayscale subpixels equals to a number of the first low-grayscale subpixels, and N is an integral multiple of 2, an integral multiple of 3, or 1.
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公开(公告)号：US20240179953A1
公开(公告)日：2024-05-30
申请号：US18084877
申请日：2022-12-20
Inventor： Jiexin ZHENG , Weiran CAO , Wei LU , Quan CHENG
IPC: H10K59/122 , H10K50/824 , H10K71/00
CPC classification number: H01L27/3246 , H01L51/5228 , H01L51/56 , H01L2227/323
Abstract: A display panel and an electronic device are provided. In the display panel, by disposing an auxiliary electrode in a first opening of a pixel definition layer, a first electrode is electrically connected to an auxiliary electrode line through the auxiliary electrode, so as to reduce a resistance of the first electrode. Therefore, uneven display due to voltage drop is remedied, so that a problem of large cathode resistance existing in a current display panel is relieved. Meanwhile, the first opening of the pixel definition layer of the present application exposes a part of a lateral wall of the auxiliary electrode. An organic light-emitting layer is cut off at a position of the first opening exposing the at least part of the lateral wall. The first electrode is electrically connected to the at least part of the lateral wall exposed by the organic light-emitting layer.
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公开(公告)号：US20240177638A1
公开(公告)日：2024-05-30
申请号：US17758066
申请日：2022-05-18
Inventor： Defang Meng
IPC: G09G3/00 , G09G3/3233
CPC classification number: G09G3/006 , G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2330/12
Abstract: The present disclosure discloses a pixel driving circuit and a control method thereof. The pixel driving circuit includes: a signal driving module for driving a light emitting diode to emit light based on connected scanning signal lines and data signal lines; a voltage detection module connected to the signal driving module for collecting a detection voltage of the light emitting diode and comparing the detection voltage with a reference voltage to generate a control signal; and a short circuit processing module connected to the signal driving module and the voltage detection module for controlling the light emitting diode based on the control signal.
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公开(公告)号：US11996506B2
公开(公告)日：2024-05-28
申请号：US17419400
申请日：2021-06-01
Inventor： Jian Xu
IPC: H01L33/62 , G09G3/32 , H01L25/075
CPC classification number: H01L33/62 , G09G3/32 , H01L25/0753
Abstract: A display panel and an electronic device are provided. The display panel includes a first power supply voltage bonding terminal and a second power supply voltage bonding terminal; a first power line and a second power line; and a plurality of light-emitting units; wherein when resistance of a first part of the first power line is greater than resistance of a second part of the first power line, resistance of a first part of the second power line is less than resistance of a second part of the second power line, alleviating non-uniform display of the panel.
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Patent Agency Ranking
公开(公告)号：US20240169877A1
公开(公告)日：2024-05-23
申请号：US17755533
申请日：2022-03-14
Inventor： Bo Hai
IPC: G09G3/20
CPC classification number: G09G3/2007 , G09G2320/0666
Abstract: The present application discloses a chromaticity adjustment method and an adjustment device of a display panel. The chromaticity adjustment method of the display panel includes: determining an initial driving voltage corresponding to a highest gray scale of the display panel; acquiring an initial white picture chromaticity of the display panel based on the initial driving voltage; determining whether the initial white picture chromaticity deviates from a target white picture chromaticity; if the initial white picture chromaticity deviates from the target white picture chromaticity, adjusting the initial driving voltage to adjust the initial white picture chromaticity.
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公开(公告)号：US20240168081A1
公开(公告)日：2024-05-23
申请号：US17771689
申请日：2022-04-22
Inventor： Jida HOU
CPC classification number: G01R31/2642 , G01R31/27
Abstract: A display panel and a burn-in test method of the display panel are disclosed. The display panel includes a data writing module, a driving module, a sensing module, a control module, and a light-emitting module. Different devices are set in each module. When the display panel is subjected to a burn-in test, a high level signal is provided to the control module, thereby controlling a test current to flow to the light-emitting module. Thereby, an influence of high current on a test performance is improved, and a comprehensive performance of the display panel is improved.
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公开(公告)号：US11991841B2
公开(公告)日：2024-05-21
申请号：US17298526
申请日：2021-04-30
Inventor： Dengqian Li , Rong Xia
IPC: H05K5/00 , C09J201/00
CPC classification number: H05K5/0021 , C09J201/00
Abstract: The present application provides a splicing display screen and a manufacturing method thereof. The splicing display screen includes a backplate. In the present application, a plurality of sub-display panels disposed on the backplate, an adhesive layer disposed between the backplate and the sub-display panels, and a plurality of first sub-surfaces configured to display images in the sub-display panels are arranged on a same plane. The adhesive layer at least corresponds to a gap between every two adjacent sub-display panels to connect every two adjacent sub-display panels.
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公开(公告)号：US11990483B2
公开(公告)日：2024-05-21
申请号：US17438956
申请日：2021-08-06
Inventor： Ziran Li
IPC: H01L27/12
CPC classification number: H01L27/1248 , H01L27/1259
Abstract: An embodiment of the present application discloses an array substrate and a manufacturing method thereof. The array substrate includes an underlay, an active layer, a gate electrode insulation layer, and a metal layer. A first through hole, second through holes, third through holes, and a fourth through hole are defined in the gate electrode insulation layer. The second through holes and third through holes are arranged at intervals such that partial regions of the active layer are shielded by the gate electrode insulation layer to prevent them from corrosion of an etching solution to guarantee a normal electrical connection of the active layer and a source electrode and a drain electrode and improve a yield rate of the array substrate.
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公开(公告)号：US11990379B2
公开(公告)日：2024-05-21
申请号：US17425675
申请日：2021-05-24
Inventor： Peijian Yan
IPC: H01L21/66 , H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L22/20 , H01L27/124 , H01L27/1244 , H01L27/1288 , G02F1/136259 , G02F1/1368
Abstract: An array substrate, a manufacturing method thereof, and a short circuit repair method are provided. The array substrate includes at least one switch unit, wherein each of the switch unit includes a first thin film transistor (TFT) set and a second TFT set, a hollow area is disposed on a first metal layer, a semiconductor layer includes a first area corresponding to the first TFT set and a second area corresponding to the second TFT set, and a vertical projection of an area between the first area and the second area on a substrate completely covers a vertical projection of the hollow area on the substrate.
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