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公开(公告)号：US10141471B2
公开(公告)日：2018-11-27
申请号：US15668138
申请日：2017-08-03
发明人： Jing-En Luan
IPC分类号： H01L31/173 , H01L31/0203 , H01L31/0232 , G01S7/481 , G01S17/02 , G01S17/08 , H01L23/00
摘要： A proximity detector device may include a first interconnect layer including a first dielectric layer, and first electrically conductive traces carried thereby, an IC layer above the first interconnect layer and having an image sensor IC, and a light source IC laterally spaced from the image sensor IC. The proximity detector device may include a second interconnect layer above the IC layer and having a second dielectric layer, and second electrically conductive traces carried thereby. The second interconnect layer may have first and second openings therein respectively aligned with the image sensor IC and the light source IC. Each of the image sensor IC and the light source IC may be coupled to the first and second electrically conductive traces. The proximity detector device may include a lens assembly above the second interconnect layer and having first and second lenses respectively aligned with the first and second openings.
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公开(公告)号：US09923020B2
公开(公告)日：2018-03-20
申请号：US14750859
申请日：2015-06-25
发明人： Jing-En Luan
IPC分类号： H01L27/146 , H04N5/369 , H01L23/00 , H04N5/225
CPC分类号： H01L27/14685 , H01L24/97 , H01L27/14618 , H01L2224/16225 , H01L2224/48095 , H01L2224/48227 , H04N5/2257 , H04N5/369
摘要： Embodiments of the present invention provide a camera module and a method of manufacturing the same, the camera module comprising a sensor assembly, at least one semiconductor substrate, and a molding compound; wherein the sensor assembly comprises a semiconductor die, a sensor circuit disposed on the top surface of the semiconductor die, and a transparent cover coupled to the semiconductor die over the top surface of the semiconductor die; wherein each semiconductor substrate is disposed around the sensor assembly in a horizontal direction; and wherein the molding compound is filled between each semiconductor substrate and the sensor assembly.
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公开(公告)号：US20170336822A1
公开(公告)日：2017-11-23
申请号：US15671657
申请日：2017-08-08
发明人： Yong Feng Liu
IPC分类号： G05F3/26
CPC分类号： G05F3/267
摘要： A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.
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公开(公告)号：US09778670B2
公开(公告)日：2017-10-03
申请号：US14267957
申请日：2014-05-02
发明人： Ni Zeng
IPC分类号： G05F1/573
CPC分类号： G05F1/573
摘要： A current limiting circuit includes a current sensing module that is configured to sense an output current of a power transistor and to generate a corresponding sensing current which is proportional to the output current. A first current limiting module coupled to the current sensing module is configured to generate a first limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a first current level. A second current limiting module coupled to the current sensing module is configured to generate a second limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a second current level. A converting module coupled to the first and second current limiting modules and the power transistor controls a gate voltage of the power transistor based at least on the first and second limiting currents.
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公开(公告)号：US20170236468A1
公开(公告)日：2017-08-17
申请号：US15585677
申请日：2017-05-03
发明人： Meng Wang , Tao Tao Huang
IPC分类号： G09G3/3225 , H03K5/12 , H03K17/687 , G09G3/36
CPC分类号： G09G3/3225 , G09G3/20 , G09G3/3208 , G09G3/3648 , G09G2300/0842 , G09G2310/0259 , G09G2310/0291 , G09G2320/041 , G09G2320/043 , G09G2330/02 , G09G2330/025 , G09G2330/028 , H02M3/158 , H03K5/12 , H03K17/04123 , H03K17/687 , H03K2217/0063 , H03K2217/0072
摘要： A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.
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公开(公告)号：US20170093348A1
公开(公告)日：2017-03-30
申请号：US15377929
申请日：2016-12-13
发明人： Ru Feng Du , Qi Yu Liu
CPC分类号： H03F1/3205 , H03F1/0205 , H03F1/305 , H03F3/183 , H03F3/185 , H03F3/187 , H03F3/211 , H03F3/2171 , H03F3/2173 , H03F3/45179 , H03F2200/03 , H03F2200/351 , H03F2203/21106 , H03F2203/45151 , H03F2203/45156 , H03G3/345 , H03G3/348 , H04R3/002
摘要： A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.
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公开(公告)号：US09531355B1
公开(公告)日：2016-12-27
申请号：US14754778
申请日：2015-06-30
发明人： Yong Feng Liu
CPC分类号： H03K5/00 , H03K5/135 , H03K2005/00202
摘要： An electronic device includes a first circuit to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal.
摘要翻译： 电子设备包括第一电路，用于响应于具有第一逻辑电平的输入信号，当接收输入电流的第一电容器两端的第一电压超过阈值电压时产生输出控制信号。 输入电流与输入信号的频率成比例。 第二电路是响应于输入信号具有第二逻辑电平而在接收输入电流的第二电容器两端的第二电压超过阈值电压时产生输出复位信号。 触发器是响应于输出控制信号而产生具有第一逻辑电平的信号输出，并且响应于输出复位信号复位并产生具有第二逻辑电平的信号输出。
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公开(公告)号：US20160373093A1
公开(公告)日：2016-12-22
申请号：US14754778
申请日：2015-06-30
发明人： Yong Feng Liu
CPC分类号： H03K5/00 , H03K5/135 , H03K2005/00202
摘要： An electronic device includes a first circuit to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal.
摘要翻译： 电子设备包括第一电路，用于响应于具有第一逻辑电平的输入信号，当接收输入电流的第一电容器两端的第一电压超过阈值电压时产生输出控制信号。 输入电流与输入信号的频率成比例。 第二电路是响应于输入信号具有第二逻辑电平而在接收输入电流的第二电容器两端的第二电压超过阈值电压时产生输出复位信号。 触发器是响应于输出控制信号而产生具有第一逻辑电平的信号输出，并且响应于输出复位信号复位并产生具有第二逻辑电平的信号输出。
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公开(公告)号：US20160357206A1
公开(公告)日：2016-12-08
申请号：US15244289
申请日：2016-08-23
发明人： Yong Feng Liu
IPC分类号： G05F1/575
摘要： A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.
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公开(公告)号：US20160329868A1
公开(公告)日：2016-11-10
申请号：US14715879
申请日：2015-05-19
发明人： Qi Yu Liu , Hong Wu Lin
CPC分类号： H03F3/183 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/03 , H03F2203/45138
摘要： A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.
摘要翻译： D类放大器包括信号处理块。 当第一差分信号的占空比大于第二差分信号的占空比时，信号处理块产生表示第一差分信号和第二差分信号之间的差的第一处理信号。 当第一差分信号的占空比小于第二差分信号的占空比时，信号处理块产生表示参考DC电平的第一处理信号。 当第二差分信号的占空比大于第一差分信号的占空比时，产生表示第二差分信号和第一差分信号之间的差的第二处理信号，并且生成表示参考DC电平的第二处理信号 当第二差分信号的占空比小于第一差分信号的占空比时。
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