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公开(公告)号:US11271570B1
公开(公告)日:2022-03-08
申请号:US16951748
申请日:2020-11-18
Inventor: Marc Gens , David Jacquet , Fabien Pousset , Elias El Haddad
Abstract: The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.
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公开(公告)号:US20210390180A1
公开(公告)日:2021-12-16
申请号:US17340164
申请日:2021-06-07
Inventor: Asif Rashid Zargar , Gilles Eyzat , Charul Jain
IPC: G06F21/55
Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.
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公开(公告)号:US20210318972A1
公开(公告)日:2021-10-14
申请号:US17229307
申请日:2021-04-13
Inventor: Jawad Benhammadi , Sylvain Meyer
Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
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公开(公告)号:US11131808B2
公开(公告)日:2021-09-28
申请号:US16549843
申请日:2019-08-23
Inventor: Charles Baudot , Sylvain Guerber , Patrick Le Maitre
Abstract: In one embodiment, a waveguide includes an upstream portion, a downstream portion, and an intermediate portion between the upstream portion and the downstream portion. A first band is disposed on an insulating layer, the first band oriented along a first direction. A first lateral strip and a second lateral strip are disposed on either side of the first band, the first lateral strip and the second lateral strip being thinner or interrupted along the intermediate portion.
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公开(公告)号:US11106618B2
公开(公告)日:2021-08-31
申请号:US16908253
申请日:2020-06-22
Applicant: STMicroelectronics (Alps) SAS
Inventor: Patrick Arnould
Abstract: A method can be used for addressing a slave integrated circuit connected to a bus. The slave integrated circuit has a default address on the bus. The method includes receiving, at the slave integrated circuit, an addressing message conveyed on the bus. The addressing message contains a replacement address. The method also includes replacing the default address within the slave integrated circuit with the replacement address upon receiving the addressing message, restarting the slave integrated circuit, and upon the restarting, assigning the replacement address as a new default address.
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公开(公告)号:US20210203226A1
公开(公告)日:2021-07-01
申请号:US17200498
申请日:2021-03-12
Applicant: STMicroelectronics (Alps) SAS
Inventor: Patrik Arno
IPC: H02M3/156
Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.
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公开(公告)号:US11005490B2
公开(公告)日:2021-05-11
申请号:US16918940
申请日:2020-07-01
Applicant: STMicroelectronics SA , STMicroelectronics (Alps) SAS
Inventor: Stéphane Le Tual , David Duperray , Jean-Pierre Blanc
Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.
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公开(公告)号:US10984845B2
公开(公告)日:2021-04-20
申请号:US16729056
申请日:2019-12-27
Inventor: Diana Moisuc , Christophe Laurencin
Abstract: In an embodiment, a method for protecting an electronic circuit includes: detecting a malfunction of the electronic circuit; executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit; and triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures. An interval between two waves of countermeasures of the plurality of waves of countermeasures is variable.
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公开(公告)号:US20210067177A1
公开(公告)日:2021-03-04
申请号:US17010351
申请日:2020-09-02
Inventor: Fabrice ROMAIN , Mathieu LISART , Patrick Arnould
Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
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公开(公告)号:US20210019448A1
公开(公告)日:2021-01-21
申请号:US16928901
申请日:2020-07-14
Inventor: Marc BENVENISTE , Fabien JOURNET , Fabrice MARINET
Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.
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