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81.发明授权公开(公告)号：US09953591B1
公开(公告)日：2018-04-24
申请号：US14500590
申请日：2014-09-29
Applicant: Apple Inc.
Inventor： Peter F. Holland , Brijesh Tripathi , Hari Ganesh R. Thirunageswaram
IPC: G09G3/36
CPC classification number: G09G3/3607 , G09G3/2048 , G09G3/3611
Abstract: Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. Each display pipeline generates dither noise for each frame in its entirety but only utilizes dither noise for the portion of the frame which is being driven to its respective portion of the display. This approach prevents visual artifacts from appearing at the dividing line between the first and second portions of the display.
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公开(公告)号：US09652816B1
公开(公告)日：2017-05-16
申请号：US14500570
申请日：2014-09-29
Applicant: Apple Inc.
Inventor： Peter F. Holland , Brijesh Tripathi , Joshua P. de Cesare , Arthur L. Spence , Christopher P. Tann , Paolo Sacchetto
CPC classification number: G06T13/00 , G06T2200/28 , G09G5/39 , G09G2330/021 , G09G2340/0435 , G09G2360/18
Abstract: Systems, apparatuses, and methods for adjusting the frame refresh rate used for driving frames to a display. A display pipeline is configured to drive a display using a reduced frame refresh rate in certain scenarios. The reduced frame refresh rate may be specified in frame packets which contain configuration data for processing corresponding frames. The display pipeline may drive idle frames to the display to generate the reduced frame refresh rate. When a touch event is detected, the display pipeline may override the reduced frame refresh rate and instead utilize a standard frame refresh rate until all of the frames corresponding to stored frame packets have been processed.
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公开(公告)号：US09495926B2
公开(公告)日：2016-11-15
申请号：US14557001
申请日：2014-12-01
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Peter F. Holland , Arthur L. Spence , Axel B. Schumacher , David A. Hartley
CPC classification number: G09G3/3614 , G06T1/20 , G06T1/60 , G09G3/3696 , G09G2320/0266 , G09G2330/021 , G09G2340/0435
Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.
Abstract translation: 用于防止显示器的显示面板上的电荷累积的系统，装置和方法。 显示管道被配置为使用可变帧刷新率驱动显示器。 显示器也可以由极性反转节奏驱动，以在背对背框上交替显示面板上的极性。 在某些情况下，如果在包含用于处理相应帧的配置数据的帧分组中指定的帧刷新率节奏可以在切换到第一帧刷新率之前以奇数帧显示在显示面板上的电荷累积 第二帧刷新率。 因此，在这些情况下，显示管线可以覆盖给定帧的帧刷新率设置，以使得以第一帧刷新率显示偶数帧。
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公开(公告)号：US09412147B2
公开(公告)日：2016-08-09
申请号：US14493755
申请日：2014-09-23
Applicant: Apple Inc.
Inventor： Peter F. Holland , Hari Ganesh R. Thirunageswaram , Jeffrey J. Irwin
CPC classification number: G06T1/20 , G06T1/60 , G06T2200/28 , G09G5/363 , G09G5/395 , G09G2320/0276 , G09G2340/0407 , G09G2340/10 , G09G2352/00 , G09G2360/121
Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.
Abstract translation: 用于处理图形数据的装置可以包括多个处理流水线，每个流水线被配置为接收和处理像素数据。 功能单元可以组合每个处理流水线的输出。 包括在给定处理流水线中的缓冲器可以被配置为响应于确定给定处理流水线不活动而存储来自功能单元的数据。 然后，缓冲器可以将存储的数据发送到存储器。
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公开(公告)号：US20160155399A1
公开(公告)日：2016-06-02
申请号：US14557001
申请日：2014-12-01
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Peter F. Holland , Arthur L. Spence , Axel B. Schumacher
CPC classification number: G09G3/3614 , G06T1/20 , G06T1/60 , G09G3/3696 , G09G2320/0266 , G09G2330/021 , G09G2340/0435
Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.
Abstract translation: 用于防止显示器的显示面板上的电荷累积的系统，装置和方法。 显示管道被配置为使用可变帧刷新率驱动显示器。 显示器也可以由极性反转节奏驱动，以在背对背框上交替显示面板上的极性。 在某些情况下，如果在包含用于处理对应帧的配置数据的帧分组中指定的帧刷新率节奏可以在切换到第一帧刷新率之前以奇数帧显示在显示面板上的电荷累积 第二帧刷新率。 因此，在这些情况下，显示管线可以覆盖给定帧的帧刷新率设置，以使得以第一帧刷新率显示偶数帧。
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Patent Agency Ranking
公开(公告)号：US20160086298A1
公开(公告)日：2016-03-24
申请号：US14493755
申请日：2014-09-23
Applicant: Apple Inc.
Inventor： Peter F. Holland , Hari Ganesh R. Thirunageswaram , Jeffrey J. Irwin
CPC classification number: G06T1/20 , G06T1/60 , G06T2200/28 , G09G5/363 , G09G5/395 , G09G2320/0276 , G09G2340/0407 , G09G2340/10 , G09G2352/00 , G09G2360/121
Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.
Abstract translation: 用于处理图形数据的装置可以包括多个处理流水线，每个流水线被配置为接收和处理像素数据。 功能单元可以组合每个处理流水线的输出。 包括在给定处理流水线中的缓冲器可以被配置为响应于确定给定处理流水线不活动而存储来自功能单元的数据。 然后，缓冲器可以将存储的数据发送到存储器。
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公开(公告)号：US20150355762A1
公开(公告)日：2015-12-10
申请号：US14296105
申请日：2014-06-04
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Manu Agarwal , Peter F. Holland
CPC classification number: G06F3/0412 , G06F3/0416 , G06F2203/04101 , G06T1/20 , H04N3/24 , H04N2101/00
Abstract: Systems, apparatuses, and methods for performing mid-frame blanking. A first portion of a frame is driven to a display and then a first mid-frame blanking interval is generated. Following this first mid-frame blanking interval, a second portion of the frame is driven to the display, followed by a second mid-frame blanking interval, followed by a third portion of the frame, and so on. Any number of mid-frame blanking intervals may be introduced in a given frame. During each mid-frame blanking interval, touch sensing is performed to detect touch events on the screen for in-cell touch type displays. For displays with touch sensors electrically separated from the display common voltage layer, special sense scan steps are performed during mid-frame blanking intervals. By performing touch sensing or special sense scan steps during a frame rather than only at the end of a frame, the performance of touch sensing is improved.
Abstract translation: 执行中帧消隐的系统，设备和方法。 帧的第一部分被驱动到显示器，然后产生第一中间帧消隐间隔。 在该第一中间帧消隐间隔之后，帧的第二部分被驱动到显示器，随后是第二中间帧消隐间隔，随后是帧的第三部分，等等。 可以在给定的帧中引入任何数量的中帧消隐间隔。 在每个中间帧消隐间隔期间，执行触摸感测以检测用于小区内触摸式显示的屏幕上的触摸事件。 对于具有与显示器公共电压层电气分离的触摸传感器的显示器，在中帧消隐间隔期间执行特殊感测扫描步骤。 通过在帧期间执行触摸感测或特殊感测扫描步骤，而不仅仅是在帧的结尾处，提高了触摸感测的性能。
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88.发明授权公开(公告)号：US09196187B2
公开(公告)日：2015-11-24
申请号：US14247373
申请日：2014-04-08
Applicant: Apple Inc.
Inventor： Peter F. Holland , Craig M. Okruhlica
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2330/022 , G09G2360/08 , G09G2360/14
Abstract: A system includes one or more video processing components and a display processing unit. The display processing unit may include one or more processing pipelines that generate read requests to fetch stored pixel data from a memory for subsequent display on a display unit. The display processing unit may also include a timing control unit that may generate an indication that indicates that the display unit will enter an inactive state. In response to receiving the indication, one or more of the video processing components may enter a low power state.
Abstract translation: 系统包括一个或多个视频处理组件和显示处理单元。 显示处理单元可以包括一个或多个处理管线，其生成读取请求以从存储器提取存储的像素数据，以便随后在显示单元上显示。 显示处理单元还可以包括定时控制单元，其可以生成指示显示单元将进入非活动状态的指示。 响应于接收到指示，一个或多个视频处理组件可以进入低功率状态。
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公开(公告)号：US20150302544A1
公开(公告)日：2015-10-22
申请号：US14258662
申请日：2014-04-22
Applicant: Apple Inc.
Inventor： Hao Chen , Benjamin K. Dodge , Peter F. Holland
IPC: G06T1/20
CPC classification number: G09G5/397 , G09G5/001 , G09G5/14 , G09G2340/0407 , G09G2340/10 , G09G2350/00 , G09G2352/00 , G09G2360/125
Abstract: Systems and methods for determining priorities of pixel fetch requests of separate requestors in a display control unit. The distance between the oldest pixel in an output buffer and the output equivalent coordinate of the oldest outstanding source pixel read request for each requestor in the display control unit is calculated. Then, a priority is assigned to each requestor based on this calculated distance. If a given requestor lags behind the other requestors based on a comparison of the distance between the oldest pixel and the output equivalent coordinate of the oldest outstanding source pixel read, then source pixel fetch requests for this given requestor are given a higher priority than source pixel fetch requests for the other requestors.
Abstract translation: 用于确定显示控制单元中单独请求者的像素提取请求的优先级的系统和方法。 计算输出缓冲器中的最旧像素与显示控制单元中每个请求者的最早未完成源像素读取请求的输出等效坐标之间的距离。 然后，基于该计算出的距离将优先级分配给每个请求者。 如果给定的请求者基于最旧的像素读取的最旧的源像素的输出等效坐标之间的距离的比较而落在其他请求者之后，则给予该给定请求者的源像素提取请求被给予比源像素更高的优先级 提取其他请求者的请求。
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公开(公告)号：US09117299B2
公开(公告)日：2015-08-25
申请号：US13889816
申请日：2013-05-08
Applicant: Apple Inc.
Inventor： Albert C. Kuo , Peter F. Holland
CPC classification number: G06T1/60 , G09G5/001 , G09G2360/12
Abstract: A system and method for efficiently scheduling memory access requests from a display controller pipeline. The display controller monitors the amount of data in the line buffers in the internal pixel-processing pipelines. The display controller waits until the amount of data in a given line buffer has fallen below an amount equal to the pixel width of the region being rendered by the internal pixel-processing pipeline before issuing memory requests to the memory controller. When the memory controller is not processing received memory requests, the memory controller transitions to a low-power state.
Abstract translation: 一种用于从显示控制器管线有效地调度存储器访问请求的系统和方法。 显示控制器监视内部像素处理流水线中的行缓冲器中的数据量。 在向存储器控制器发出存储器请求之前，显示控制器等待直到给定行缓冲器中的数据量已经下降到等于由内部像素处理流水线呈现的区域的像素宽度的量的量。 当存储器控制器不处理接收到的存储器请求时，存储器控制器转换到低功率状态。
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