公开(公告)号：US20240428494A1

公开(公告)日：2024-12-26

申请号：US18749032

申请日：2024-06-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Karthik Mohan Kumar ,  Michael Mantor ,  Pedro Antonio Pena ,  Archana Ramalingam

IPC: G06T13/40 ,  H04N19/124

Abstract: Systems and techniques for generating and animating non-player characters (NPCs) within virtual digital environments are provided. Multimodal input data is received that comprises a plurality of input modalities for interaction with an NPC having a set of body features and a set of facial features. The multimodal input data is processed through one or more neural networks to generate animation sequences for both the body features and facial features of the NPC. Generating such animation sequences includes disentangling the multimodal input data to generate substantially disentangled latent representations, combining these representations with the multimodal input data, and using a large-language model (LLM) to generate speech data for the NPC. Further processing using reverse diffusion generates face vertex displacement data and joint trajectory data based on the combined representation and generated speech data. The face vertex displacement data, joint trajectory data, and speech data are used to produce an animated representation of the NPC, which is then provided to environment-specific adapters to animate the NPC within a virtual digital environment.

公开(公告)号：US12153957B2

公开(公告)日：2024-11-26

申请号：US17957714

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

IPC: G06F9/48

Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

公开(公告)号：US20240192994A1

公开(公告)日：2024-06-13

申请号：US18127395

申请日：2023-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad Ashkar ,  Michael Mantor ,  Rex Eldon McCrary ,  Yi Luo ,  Manu Rastogi ,  James Robert Klobcar

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5027 ,  G06F9/4881

Abstract: Techniques for implementing accelerated draw indirect fetching are disclosed. A fetch accelerator enables streamlined data fetching by looping internally and filling a draw queue for a micro engine. By using a dedicated fetch accelerator rather than processing data fetches separately and individually using a conventional processor, significant processing overhead is eliminated and computational latency is reduced. Additionally, different types of aligned or unaligned data structures are usable with equivalent or nearly equivalent performance.

公开(公告)号：US11854139B2

公开(公告)日：2023-12-26

申请号：US17564160

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Konstantin Igorevich Shkurko ,  Michael Mantor

IPC: G06T15/06 ,  G06T15/08 ,  G06F9/48 ,  G06T17/10 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06F9/4881 ,  G06T1/20 ,  G06T15/005 ,  G06T15/08 ,  G06T17/10

Abstract: A processing unit employs a hardware traversal engine to traverse an acceleration structure such as a ray tracing structure. The hardware traversal engine includes one or more memory modules to store state information and other data used for the structure traversal, and control logic to execute a traversal process based on the stored data and based on received information indicating a source node of the acceleration structure to be used for the traversal process. By employing a hardware traversal engine, the processing unit is able to execute the traversal process more quickly and efficiently, conserving processing resources and improving overall processing efficiency.

公开(公告)号：US11768664B2

公开(公告)日：2023-09-26

申请号：US16591031

申请日：2019-10-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bin He ,  Michael Mantor ,  Jiasheng Chen

IPC: G06F7/57 ,  G06F7/544 ,  G06F9/38 ,  G06F7/483

CPC classification number: G06F7/57 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/3818 ,  G06F2207/3824

Abstract: A graphics processing unit (GPU) implements operations, with associated op codes, to perform mixed precision mathematical operations. The GPU includes an arithmetic logic unit (ALU) with different execution paths, wherein each execution path executes a different mixed precision operation. By implementing mixed precision operations at the ALU in response to designate op codes that delineate the operations, the GPU efficiently increases the precision of specified mathematical operations while reducing execution overhead.

公开(公告)号：US11762658B2

公开(公告)日：2023-09-19

申请号：US16581252

申请日：2019-09-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bin He ,  Michael Mantor ,  Jiasheng Chen ,  Jian Huang

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F9/54

CPC classification number: G06F9/30036 ,  G06F9/30101 ,  G06F9/3877 ,  G06F9/544 ,  G06F17/16

Abstract: A processing unit such as a graphics processing unit (GPU) includes a plurality of vector signal processors (VSPs) that include multiply/accumulate elements. The processing unit also includes a plurality of registers associated with the plurality of VSPs. First portions of first and second matrices are fetched into the plurality of registers prior to a first round that includes a plurality of iterations. The multiply/accumulate elements perform matrix multiplication and accumulation on different combinations of subsets of the first portions of the first and second matrices in the plurality of iterations prior to fetching second portions of the first and second matrices into the plurality of registers for a second round. The accumulated results of multiplying the first portions of the first and second matrices are written into an output buffer in response to completing the plurality of iterations.

公开(公告)号：US20230289191A1

公开(公告)日：2023-09-14

申请号：US18128642

申请日：2023-03-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh LAGUDU ,  Allen H. Rush ,  Michael Mantor ,  Arun Vaidyanathan Ananthanarayan ,  Prasad Nagabhushanamgari ,  Maxim V. Kazakov

IPC: G06F9/38 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F9/3887 ,  G06F13/28 ,  G06F13/4027

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

公开(公告)号：US11635967B2

公开(公告)日：2023-04-25

申请号：US17032307

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh Lagudu ,  Allen H. Rush ,  Michael Mantor ,  Arun Vaidyanathan Ananthanarayan ,  Prasad Nagabhushanamgari ,  Maxim V. Kazakov

IPC: G06F15/80 ,  G06F9/38 ,  G06F13/28 ,  G06F13/40

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

公开(公告)号：US11630667B2

公开(公告)日：2023-04-18

申请号：US16697660

申请日：2019-11-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jiasheng Chen ,  Bin He ,  Jian Huang ,  Michael Mantor

IPC: G06F9/30 ,  G06F9/48

Abstract: A processor includes a plurality of vector sub-processors (VSPs) and a plurality of memory banks dedicated to respective VSPs. A first memory bank corresponding to a first VSP includes a first plurality of high vector general purpose register (VGPR) banks and a first plurality of low VGPR banks corresponding to the first plurality of high VGPR banks. The first memory bank further includes a plurality of operand gathering components that store operands from respective high VGPR banks and low VGPR banks. The operand gathering components are assigned to individual threads while the threads are executed by the first VSP.

公开(公告)号：US11494192B2

公开(公告)日：2022-11-08

申请号：US16860842

申请日：2020-04-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.

Inventor： Jiasheng Chen ,  YunXiao Zou ,  Bin He ,  Angel E. Socarras ,  QingCheng Wang ,  Wei Yuan ,  Michael Mantor

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06F15/76

Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.