公开(公告)号：US11170843B2

公开(公告)日：2021-11-09

申请号：US16824663

申请日：2020-03-19

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Ettore Amirante

IPC: G11C8/00 ,  G11C11/4097 ,  G11C5/02 ,  G11C11/408 ,  G11C11/4094

Abstract: Various implementations described herein are related to a device having a bitcell. The device may include horizontal bitlines coupled to the bitcell. The horizontal bitlines may include multiple first read bitlines disposed in a horizontal direction with respect to the bitcell. The device may include vertical bitlines coupled to the bitcell. The vertical bitlines may include multiple second read bitlines disposed in a vertical direction with respect to the bitcell.

公开(公告)号：US11133043B2

公开(公告)日：2021-09-28

申请号：US16783104

申请日：2020-02-05

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C8/00 ,  G11C8/10 ,  G11C7/06 ,  G11C7/22 ,  G11C7/10 ,  G11C7/12

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.

公开(公告)号：US11017142B1

公开(公告)日：2021-05-25

申请号：US17010630

申请日：2020-09-02

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Shruti Aggarwal ,  Mohit Chanana ,  Hsin-Yu Chen ,  Kyung Woo Kim

IPC: G06F30/343 ,  G06F30/337 ,  G06F30/20 ,  G06F1/28 ,  G06F119/12 ,  G06F119/06 ,  G06F30/3308

Abstract: According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.

公开(公告)号：US20210074353A1

公开(公告)日：2021-03-11

申请号：US17101610

申请日：2020-11-23

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Teresa Louise McLaurin ,  Frank David Frederick ,  Richard Slobodnik ,  Yew Keong Chong

IPC: G11C11/419 ,  G11C7/22 ,  H03K19/1776 ,  G11C7/10

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

公开(公告)号：US10796053B2

公开(公告)日：2020-10-06

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, Jr. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50 ,  G06F30/39 ,  G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20200286548A1

公开(公告)日：2020-09-10

申请号：US16294577

申请日：2019-03-06

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, JR. ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.

公开(公告)号：US10741227B2

公开(公告)日：2020-08-11

申请号：US16058375

申请日：2018-08-08

Applicant: Arm Limited

Inventor： Kumaraswamy Ramanathan ,  Peixuan Tan ,  Andy Wangkun Chen

IPC: G11C8/00 ,  G11C7/22 ,  H03K3/037

Abstract: Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.

公开(公告)号：US10574236B2

公开(公告)日：2020-02-25

申请号：US15682327

申请日：2017-08-21

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Cagla Cakir

IPC: H03K19/0185 ,  G11C7/10 ,  H03K3/0233 ,  G11C8/06 ,  H03K3/356 ,  G11C5/14

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include level shifting circuitry for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The integrated circuit may include input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals. The integrated circuit may include bypass switching circuitry for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.

公开(公告)号：US20200051602A1

公开(公告)日：2020-02-13

申请号：US16058375

申请日：2018-08-08

Applicant: Arm Limited

Inventor： Kumaraswamy Ramanathan ,  Peixuan Tan ,  Andy Wangkun Chen

IPC: G11C7/22 ,  H03K3/037

Abstract: Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.

公开(公告)号：US20190325947A1

公开(公告)日：2019-10-24

申请号：US15956724

申请日：2018-04-18

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Teresa Louise McLaurin ,  Frank David Frederick ,  Richard Slobodnik ,  Yew Keong Chong

IPC: G11C11/419 ,  G11C7/22 ,  G11C7/10 ,  H03K19/177

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.