公开(公告)号：US20170294461A1

公开(公告)日：2017-10-12

申请号：US15325402

申请日：2016-03-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng CAO ,  Feng ZHANG ,  Bin ZHANG ,  Xiaolong HE ,  Zhengliang LI ,  Wei ZHANG ,  Feng GUAN ,  Jincheng GAO

IPC: H01L27/12

CPC classification number: H01L27/1262 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.

公开(公告)号：US20170005110A1

公开(公告)日：2017-01-05

申请号：US15150549

申请日：2016-05-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng CAO ,  Feng ZHANG ,  Bin ZHANG ,  Xiaolong HE ,  Jincheng GAO ,  Qi YAO ,  Zhengliang LI ,  Xiangchun KONG

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/124 ,  H01L29/41733 ,  H01L29/42384

Abstract: An array substrate and a display device are disclosed. The array substrate includes a peripheral area in which a plurality of gate electrode material lines, a plurality of source-drain electrode material lines and a plurality of first metal lines are disposed. Overlapping areas are provided between or among the gate electrode material lines, the source-drain material lines and the first metal lines; a number of the overlapping areas of the source-drain material lines and the first metal lines is less than a number of the overlapping areas of the source-drain material lines and the gate electrode material lines; the gate electrode material lines, the source-drain material lines and the first metal lines are configured as connecting lines of circuits in the peripheral area.

Abstract translation: 公开了阵列基板和显示装置。 阵列基板包括其中设置多个栅电极材料线，多个源极 - 漏极电极材料线和多个第一金属线的外围区域。 在栅电极材料线，源极 - 漏极材料线和第一金属线之间或之间提供重叠区域; 源极 - 漏极材料线和第一金属线的重叠区域的数量少于源极 - 漏极材料线和栅极材料线的重叠面积的数量; 栅电极材料线，源极 - 漏极材料线和第一金属线构成为周边区域中的电路的连接线。

公开(公告)号：US20160011457A1

公开(公告)日：2016-01-14

申请号：US14421944

申请日：2014-07-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng ZHANG ,  Guanbao HUI ,  Zhanfeng CAO ,  Qi YAO

IPC: G02F1/1335

CPC classification number: G02F1/133516 ,  G02F1/133512 ,  G02F1/136209 ,  G02F2001/136222 ,  H01L21/0274 ,  H01L27/1288 ,  H01L27/3295 ,  H01L51/5012

Abstract: A fabrication method of a substrate, relates to a field of a display technology, which can avoid a deviation between a line width of a black matrix or a color filter layer actually fabricated and a preset line width, so that the black matrix can just completely shield thin film transistor, a data line and a gate line, and meanwhile the black matrix or the color filter layer more refined are obtained, which improves the display effect of the liquid crystal display. The fabrication method of the substrate comprises: forming a to-be-treated layer, forming a light-shielding layer on the to-be-treated layer, and forming a pattern of the light-shielding layer by a patterning process, wherein the light-shielding layer is made of metal; performing a patterning process on the to-be-treated layer by using the pattern of the light-shielding layer as a mask; and removing the light-shielding layer.

Abstract translation: 基板的制造方法涉及显示技术的领域，其可以避免实际制造的黑矩阵或滤色器层的线宽与预设线宽之间的偏差，使得黑矩阵可以完全 屏蔽薄膜晶体管，数据线和栅极线，同时获得更细化的黑矩阵或滤色器层，从而提高了液晶显示器的显示效果。 基板的制造方法包括：形成被处理层，在待处理层上形成遮光层，并通过图案化工艺形成遮光层的图案，其中光 屏蔽层由金属制成; 通过使用遮光层的图案作为掩模对被处理层进行图案化处理; 并且去除遮光层。

公开(公告)号：US20150372011A1

公开(公告)日：2015-12-24

申请号：US14435877

申请日：2014-09-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng ZHANG ,  Zhanfeng CAO ,  Qi YAO ,  Shi SHU

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G02F1/134363 ,  G02F1/136209 ,  G02F1/136227 ,  G02F2001/136222 ,  H01L27/1262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array substrate and manufacturing method thereof, and a display device are capable of preventing light reflection from a drain electrode, and guaranteeing the display effect of the display device. The array substrate includes a drain electrode of a thin film transistor unit, an insulating layer and a pixel electrode. The insulating layer is located between the drain electrode and the pixel electrode, and has a via hole formed therein, and the drain electrode and the pixel electrode are connected through the via hole. A surface of the pixel electrode at the via hole is a rough face.

Abstract translation: 阵列基板及其制造方法以及显示装置能够防止来自漏电极的光反射，并且保证显示装置的显示效果。 阵列基板包括薄膜晶体管单元的漏电极，绝缘层和像素电极。 绝缘层位于漏电极和像素电极之间，并且其中形成有通孔，漏电极和像素电极通过通孔连接。 通孔处的像素电极的表面是粗糙的面。

公开(公告)号：US20150236056A1

公开(公告)日：2015-08-20

申请号：US14447928

申请日：2014-07-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chuanxiang XU ,  Shi SHU ,  Yonglian QI ,  Feng ZHANG

IPC: H01L27/12

CPC classification number: H01L27/1262 ,  G02F1/136227 ,  G02F2001/136222 ,  H01L27/124

Abstract: The present invention discloses an array substrate and a manufacturing method for the same, and a display device. By adopting the manufacturing method for the array substrate provided by the embodiments of the present invention, via holes with relatively small hole sizes in a color resin layer are realized, so that the aperture ratio of pixels is improved. The manufacturing method for the array substrate includes: forming thin film transistors on a substrate; forming a color resin layer on the substrate on which the thin film transistors are formed; forming a first light-blocking layer with a light-shielding effect on the color resin layer, the photolithographic resolution of the first light-blocking layer being greater than that of the color resin layer; and performing a patterning process on the first light-blocking layer and the color resin layer to form via holes in the color resin layer.

Abstract translation: 本发明公开了一种阵列基板及其制造方法以及显示装置。 通过采用由本发明实施例提供的阵列基板的制造方法，可以实现在彩色树脂层中具有较小孔尺寸的通孔，从而提高像素的开口率。 阵列基板的制造方法包括：在基板上形成薄膜晶体管; 在其上形成有薄膜晶体管的基板上形成着色树脂层; 在着色树脂层上形成具有遮光效果的第一遮光层，第一遮光层的光刻分辨率大于着色树脂层的光刻分辨率; 并对第一遮光层和着色树脂层进行图案化处理，以在着色树脂层中形成通孔。

公开(公告)号：US20140077207A1

公开(公告)日：2014-03-20

申请号：US14027413

申请日：2013-09-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tao GAO ,  Weifeng ZHOU ,  Feng ZHANG ,  Zhijun LV

IPC: H01L27/12

CPC classification number: H01L27/1288 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/136236 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124

Abstract: Embodiments of the present invention relate to an array substrate and a manufacturing method thereof. The manufacturing method comprises: step 1: forming a gate line, a gate electrode, a first insulating layer, an active layer and ohmic contact layers on a base substrate by a first patterning process using a gray-tone or half-tone mask, in which the active layer between the ohmic contact layers corresponds to a channel region; step 2: forming a second insulating layer and a pixel electrode film on the base substrate obtained after the step 1 by a second patterning process using a gray-tone or half-tone mask; and step 3: forming a drain electrode, a source electrode, a data line and a passivation layer on the base substrate obtained after the step 2 by a third patterning process using a gray-tone or half-tone mask.

Abstract translation: 本发明的实施例涉及一种阵列基板及其制造方法。 制造方法包括：步骤1：通过使用灰色调或半色调掩模的第一图案化处理，在基底基板上形成栅极线，栅电极，第一绝缘层，有源层和欧姆接触层， 其中欧姆接触层之间的有源层对应于沟道区; 步骤2：通过使用灰色调或半色调掩模的第二图案化处理，在步骤1之后获得的基底基板上形成第二绝缘层和像素电极膜; 步骤3：通过使用灰色调或半色调掩模的第三图案化处理，在步骤2之后获得的基底基板上形成漏电极，源电极，数据线和钝化层。