公开(公告)号：US20100202195A1

公开(公告)日：2010-08-12

申请号：US12763750

申请日：2010-04-20

申请人： Pradeep Ramani ,  John D. Porter

发明人： Pradeep Ramani ,  John D. Porter

IPC分类号： G11C11/00 ,  G11C7/22

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： The present disclosure includes devices and methods for operating resistance variable memory cells. One or more embodiments include applying a programming signal to a resistance variable material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.

摘要翻译： 本公开包括用于操作电阻变量存储单元的装置和方法。 一个或多个实施例包括将编程信号施加到存储器单元的电阻可变材料，以及根据特定减量的数量连续地减小所施加的编程信号的尾部的幅度。 特定减量数量的大小和持续时间对应于特定的编程值。

公开(公告)号：US20090279374A1

公开(公告)日：2009-11-12

申请号：US12118420

申请日：2008-05-09

申请人： John D. Porter

发明人： John D. Porter

IPC分类号： G11C5/14

CPC分类号： G11C13/0011 ,  G11C5/025 ,  G11C5/14 ,  G11C7/12 ,  G11C11/5621 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/79 ,  Y10T29/49117

摘要： The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.

摘要翻译： 本公开包括用于编程存储器的装置，方法和系统，例如电阻变量存储器。 一个实施例可以包括电阻可变存储单元的阵列，其中电阻可变存储单元耦合到一个或多个数据线，连接到阵列的第一侧的行解码器，连接到阵列第二侧的列解码器 ，其中所述第二侧与所述第一侧相邻，位于所述行解码器和所述列解码器附近的间隙以及被配置为在编程操作期间控制与一个或多个未选择的存储器单元相关联的反向偏置电压的钳位电路，其中， 钳位电路位于间隙中，并且选择性地耦合到一个或多个数据线。

公开(公告)号：US07190610B2

公开(公告)日：2007-03-13

申请号：US11216665

申请日：2005-08-31

申请人： John D. Porter ,  William N. Thompson

发明人： John D. Porter ,  William N. Thompson

IPC分类号： G11C11/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104

摘要： An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

摘要翻译： 提供具有一对交叉耦合CMOS反相器的SRAM存储单元。 形成每个CMOS反相器的上拉晶体管的源极通过其中形成各自的衬底的寄生电阻耦合到V CC。 因此，p型上拉晶体管的源极总是处于小于或等于N阱的电位的电位，使得寄生PNP晶体管的发射极 - 基极结不能变为正向偏置，并且闭锁不能 发生。

公开(公告)号：US07046038B2

公开(公告)日：2006-05-16

申请号：US10336386

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K19/0175

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

摘要翻译： 本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。 根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。 另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。 本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。 与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。 此外，实际上所有的输入门加载都用于传播的快速边缘。 此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

公开(公告)号：US07018889B2

公开(公告)日：2006-03-28

申请号：US10869128

申请日：2004-06-16

申请人： John D. Porter ,  William N. Thompson

发明人： John D. Porter ,  William N. Thompson

IPC分类号： H01L21/8234 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  G11C11/412

摘要： An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

摘要翻译： 提供具有一对交叉耦合CMOS反相器的SRAM存储单元。 形成每个CMOS反相器的上拉晶体管的源极通过其中形成各自的衬底的寄生电阻耦合到V CC。 因此，p型上拉晶体管的源极总是处于小于或等于N阱的电位的电位，使得寄生PNP晶体管的发射极 - 基极结不能变为正向偏置，并且闭锁不能 发生。

公开(公告)号：US06958661B2

公开(公告)日：2005-10-25

申请号：US10409460

申请日：2003-04-08

申请人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

发明人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

IPC分类号： H03H11/28 ,  H03H17/02 ,  H03H11/30

CPC分类号： G11C7/1051 ,  G11C7/1069 ,  H03H7/40 ,  H03H11/245 ,  H03H11/28 ,  H03H17/0263

摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

摘要翻译： 公开了一种从值范围内找到未知值的方法，其将范围划分为加权子范围，然后从该范围内的任意搜索值开始，执行多个简单比较，以确定每个子范围的值， 导致与目标值匹配。 该方法还可以检测目标值在范围之外的情况。 在一个实施例中，将在值范围内找到未知值的方法应用于阻抗匹配。 在本实施例中，集成电路上的引脚的输出阻抗与连接到其的负载的阻抗自动匹配。 输出驱动器具有可控阻抗，可以在特定阻抗范围内进行调节，以匹配驱动的外部负载阻抗。

公开(公告)号：US06917222B2

公开(公告)日：2005-07-12

申请号：US10336527

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K19/017 ,  H03K19/00

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

摘要翻译： 本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。 根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。 另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。 本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。 与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。 此外，实际上所有的输入门加载都用于传播的快速边缘。 另外，如本文公开的复位网络由至少两个门缓冲，从而减少由偏斜逻辑器件的输入或输出所看到的负载。

公开(公告)号：US06809968B2

公开(公告)日：2004-10-26

申请号：US10368068

申请日：2003-02-18

申请人： Kenneth W. Marr ,  John D. Porter

发明人： Kenneth W. Marr ,  John D. Porter

IPC分类号： G11C700

CPC分类号： G11C11/412 ,  G11C5/147 ,  G11C11/417

摘要： Systems and methods are provided for a temperature-compensated threshold voltage VT. The stability problems associated with temperature changes are reduced for LL4TCMOS SRAM cells by providing a temperature-compensated VTN. According to one embodiment, a temperature-based modulation of a VBB potential back-biases a triple-well transistor with a temperature-compensated voltage to provide the pull-down transistor with a temperature-compensated VTN that is flat or relatively flat with respect to temperature. One embodiment provides a bias generator, including a charge pump coupled to a body terminal of the transistor(s), and a comparator coupled to the charge pump. The comparator includes a first input that receives a reference voltage, a second input that receives a VT-dependent voltage, and an output that presents a control signal to the charge pump and causes the charge pump to selectively charge the body terminal of the transistor to compensate for temperature changes.

摘要翻译： 为温度补偿阈值电压VT提供系统和方法。 通过提供温度补偿VTN，LL4TCMOS SRAM单元的温度变化相关的稳定性问题减少了。 根据一个实施例，VBB电位的基于温度的调制利用温度补偿电压对三阱晶体管进行背偏置，以向下拉晶体管提供相对于平坦或相对平坦的温度补偿VTN 温度。 一个实施例提供了一种偏置发生器，包括耦合到晶体管的主体端子的电荷泵和耦合到电荷泵的比较器。 比较器包括接收参考电压的第一输入端，接收VT相关电压的第二输入端和向电荷泵呈现控制信号的输出，并使电荷泵有选择地将晶体管的体电极充电至 补偿温度变化。

公开(公告)号：US06724218B2

公开(公告)日：2004-04-20

申请号：US10336355

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K190175

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

摘要翻译： 本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。 根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。 另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。 本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。 与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。 此外，实际上所有的输入门加载都用于传播的快速边缘。 此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

公开(公告)号：US06545560B1

公开(公告)日：2003-04-08

申请号：US09924658

申请日：2001-08-08

申请人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

发明人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

IPC分类号： H03H1130

CPC分类号： G11C7/1051 ,  G11C7/1069 ,  H03H7/40 ,  H03H11/245 ,  H03H11/28 ,  H03H17/0263

摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.