利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

98 条记录 (耗时 0.032 秒)

    Content deskewing for multichannel synchronization
    81.
    发明授权
    Content deskewing for multichannel synchronization 有权
    多通道同步的内容去歪斜

    公开(公告)号：US07549074B2

    公开(公告)日：2009-06-16

    申请号：US11143370

    申请日：2005-06-02

    申请人： Ravikumar K. Charath ,  Vladimir Sindalovsky ,  Lane A. Smith

    发明人： Ravikumar K. Charath ,  Vladimir Sindalovsky ,  Lane A. Smith

    IPC分类号： G06F1/12

    CPC分类号： H03M9/00 ,  H04J3/0632 ,  H04J3/0685

    摘要： The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments determine whether a data alignment signal has been written, for each data channel of the plurality of data channels, such as a comma character. When a data alignment signal has been written in a data channel of the plurality of data channels, the embodiments determine a corresponding channel location of the data alignment signal for each data channel having the data alignment signal. When each data channel of the plurality of data channels has the data alignment signal, and when the data alignment signal is to be read on a next read cycle in at least one data channel, the various embodiments move a corresponding read pointer for each data channel of the plurality of data channels to the corresponding channel location of the data alignment signal. The data alignment signal is then read in all channels during the next read cycle, followed by subsequent reading of deskewed or otherwise synchronized data, such as for conversion of parallel data into serial data for subsequent data transmission.

    摘要翻译： 本发明的各种实施例提供了一种用于数据同步的多个数据信道之间的数据内容偏移校正的装置，系统和方法。 各种实施例针对多个数据信道中的每个数据信道（诸如逗号字符）确定是否已经写入数据对准信号。 当数据对准信号已被写入多个数据通道的数据通道时，这些实施例为具有数据对准信号的每个数据通道确定数据对准信号的相应通道位置。 当多个数据信道的每个数据信道具有数据对准信号时，并且当在至少一个数据信道中在下一个读取周期读取数据对准信号时，各种实施例移动每个数据信道的相应读指针 多个数据信道的数据对准信号的相应信道位置。 然后在下一个读取周期期间在所有通道中读取数据对齐信号，随后读取去偏移或以其他方式同步的数据，例如用于将并行数据转换为串行数据以用于后续数据传输。

    Parallel trimming method and apparatus for a voltage controlled delay loop
    82.
    发明授权
    Parallel trimming method and apparatus for a voltage controlled delay loop 有权
    用于电压控制延迟回路的平行修整方法和装置

    公开(公告)号：US07495494B2

    公开(公告)日：2009-02-24

    申请号：US11141703

    申请日：2005-05-31

    申请人： Ronald L. Freyman ,  Mohammad S. Mobin ,  Vladimir Sindalovsky ,  Lane A. Smith

    发明人： Ronald L. Freyman ,  Mohammad S. Mobin ,  Vladimir Sindalovsky ,  Lane A. Smith

    IPC分类号： H03H11/26

    CPC分类号： H03L7/0814 ,  H04L7/0337

    摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.

    摘要翻译： 提供了一种用于电压控制延迟环路的并行修整方法和装置。 电压控制延迟环中的多个延迟单元被修整。 每个延迟单元包括延迟元件和锁存缓冲器。 参考信号被施加到每个延迟单元，并且识别与每个延迟单元相关联的边缘（例如上升沿或下降沿）的位置。 然后通过调整相应的锁存缓冲器的修整设置来对准延迟单元的边缘。

    Multiple phase detection for delay loops
    87.
    发明授权
    Multiple phase detection for delay loops 有权
    延迟环路的多相检测

    公开(公告)号：US07212048B2

    公开(公告)日：2007-05-01

    申请号：US11138703

    申请日：2005-05-26

    申请人： Peter C. Metz ,  Vladimir Sindalovsky ,  Lane A. Smith

    发明人： Peter C. Metz ,  Vladimir Sindalovsky ,  Lane A. Smith

    IPC分类号： H03L7/06

    CPC分类号： H03L7/07 ,  H03L7/087 ,  H03L7/097 ,  H03L7/0998 ,  H04L7/033

    摘要： A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.

    摘要翻译： 电路（例如，接收器）具有延迟环路（例如，电压控制的延迟环路）和至少两个相位检测器（PD），其中每个PD比较由延迟环路产生的不同的时钟信号对。 然后使用不同PD的输出来产生用于调整由延迟环路中的延迟元件提供的延迟的控制信号。 在一个实现中，控制信号指示仅当两个PD同意该调整时才应进行延迟调整。 这种多PD技术可以减少由延迟环使用的参考时钟信号中的非50％占空比产生其多个时钟信号的抖动。

    Method and apparatus for automatic clock alignment
    88.
    发明申请
    Method and apparatus for automatic clock alignment 有权
    自动时钟对准的方法和装置

    公开(公告)号：US20070002992A1

    公开(公告)日：2007-01-04

    申请号：US11174228

    申请日：2005-07-01

    申请人： Vladimir Sindalovsky ,  Lane Smith

    发明人： Vladimir Sindalovsky ,  Lane Smith

    IPC分类号： H03D3/24

    CPC分类号： H03L7/07 ,  H03L7/0814 ,  H04L7/0337

    摘要： The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the PLL frequency relative to data sampling points Si and transition sampling points Ti. In particular, these offsets are controlled by both coarse and fine adjustments. Typically CDR circuits employ feedback phase control information being supplied to the VCDL. The above described adjustments result in these phase control signals having an arbitrary and time-changing relation to the PLL clock. By properly selecting an appropriate edge of the PLL clock signal, the present invention synchronizes these phase control signals into the PLL clock domain in order to apply VCDL control in a synchronous manner.

    摘要翻译： 本发明使在不同时钟域中产生和使用的信号同步。 本发明可应用于CDR电路，其中通过从相对于数据采样点S 1和N 2的转换采样点控制来自PLL频率的相位偏移来实现多相时钟到输入数据相位的相位调整 T 。 特别地，这些偏移由粗调和微调两者来控制。 通常，CDR电路使用提供给VCDL的反馈相位控制信息。 上述调整导致这些相位控制信号具有与PLL时钟的任意和时变关系。 通过适当地选择PLL时钟信号的适当边沿，本发明将这些相位控制信号同步到PLL时钟域中，以便以同步方式应用VCDL控制。

    Serializer deserializer (SERDES) testing
    89.
    发明申请
    Serializer deserializer (SERDES) testing 有权

    公开(公告)号：US20060176943A1

    公开(公告)日：2006-08-10

    申请号：US11051801

    申请日：2005-02-04

    申请人： Vladimir Sindalovsky ,  Lane Smith

    发明人： Vladimir Sindalovsky ,  Lane Smith

    IPC分类号： H04B17/00

    CPC分类号： G01R31/31716

    摘要： The various embodiments of the invention provide an apparatus, system and method of testing a serializer and deserializer data communication apparatus (SERDES). The serializer and deserializer data communication apparatus has a plurality of serialize data communication channels adapted to convert parallel data to serial data and a plurality of deserialize data communication channels adapted to convert serial data to parallel data. An exemplary method provides for coupling an output of a serialize data communication channel and an input of a deserialize data communication channel to provide a serial data loop-back connection and coupling an output of a deserialize data communication channel and an input of a serialize data communication channel to provide a parallel data loop-back connection. Input test data is provided to a first serialize or deserialize data communication channel, and is successively serialized and deserialized through each corresponding serialize data communication channel and deserialize data communication channel to provide output test data. The output test data and the input test data are then compared, with SERDES devices having acceptable or unacceptable bit error rates respectively designated as passed or failed.

    Voltage controlled delay loop and method with injection point control
    90.
    发明申请
    Voltage controlled delay loop and method with injection point control 有权
    电压控制延时回路和注入点控制方法

    公开(公告)号：US20060114039A1

    公开(公告)日：2006-06-01

    申请号：US10999900

    申请日：2004-11-30

    申请人： Ronald Freyman ,  Vladimir Sindalovsky ,  Lane Smith

    发明人： Ronald Freyman ,  Vladimir Sindalovsky ,  Lane Smith

    IPC分类号： H03L7/00

    CPC分类号： H03L7/10 ,  H03L7/0814 ,  H03L7/087 ,  H04L7/0337

    摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.

    摘要翻译： 公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。 电压控制延迟环路产生具有相似频率和不同相位的时钟信号。 电压控制延迟环包括多个延迟元件; 以及输入，其选择性地将参考时钟注入到所述多个延迟元件中的任一个中。 多个延迟元件串联连接，例如循环。 在一个示例性实现中，每个延迟元件具有相关联的多路复用器，其选择参考时钟之一和来自先​​前延迟元件的信号。