公开(公告)号：US07560345B2

公开(公告)日：2009-07-14

申请号：US11749775

申请日：2007-05-17

申请人： Terence B. Hook ,  Jeffrey Scott Zimmerman

发明人： Terence B. Hook ,  Jeffrey Scott Zimmerman

IPC分类号： H01L21/336

CPC分类号： H01L27/0251 ,  G06F17/5045 ,  H01L21/84

摘要： A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting a element across the respective source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. The method includes connecting compensating conductors to an element to eliminate potential charging damage.

摘要翻译： 一种用于在具有硅绝缘体（SOI）晶体管的集成电路设计的制造期间防止充电损坏的方法。 该方法通过向IC设计分配区域来防止在处理到IC器件的栅极期间的充电损坏，使得位于区域内的器件具有电独立的网络，识别可能在源极或漏极之间具有电压差的器件，以及栅极 作为给定区域内的易感设备，并且将元件连接在相应的源极或漏极以及每个敏感器件的栅极之间，使得元件位于该区域内。 该方法包括将补偿导体连接到元件以消除潜在的充电损坏。

公开(公告)号：US07300807B2

公开(公告)日：2007-11-27

申请号：US10709109

申请日：2004-04-14

申请人： Douglas D Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

发明人： Douglas D Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

IPC分类号： H01L21/66

CPC分类号： H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

摘要翻译： 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。

公开(公告)号：US07087470B2

公开(公告)日：2006-08-08

申请号：US10873012

申请日：2004-06-21

申请人： Brent A. Anderson ,  Terence B. Hook

发明人： Brent A. Anderson ,  Terence B. Hook

IPC分类号： H01L29/72

CPC分类号： H01L21/823857

摘要： A semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, at least one of the one or more FETs of the first polarity having a gate dielectric having a thickness different from a thickness of a gate dielectric of at least one of the one or more FETs of the second polarity.

摘要翻译： 一种半导体器件和半导体器件的制造方法，所述半导体器件包括：第一极性的一个或多个FET和具有第二极性和相反极性的一个或多个FET，所述一个或多个第一极性的FET中的至少一个 具有不同于所述第一极性的所述一个或多个FET中的至少一个的栅极电介质的厚度的栅极电介质。

公开(公告)号：US06700163B2

公开(公告)日：2004-03-02

申请号：US09683278

申请日：2001-12-07

申请人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

发明人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

IPC分类号： H01L2976

CPC分类号： H01L21/823871 ,  H01L21/823842

摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

摘要翻译： 本文公开了选择性硅化半导体结构及其制造方法。 半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物 区。 这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。 在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

公开(公告)号：US06339018B1

公开(公告)日：2002-01-15

申请号：US09521719

申请日：2000-03-09

申请人： Arne W. Ballantine ,  Terence B. Hook

发明人： Arne W. Ballantine ,  Terence B. Hook

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L29/665

摘要： A method and structure for preventing device leakage. The method and structure includes forming a blocking layer of preferably nitride over a junction between a source/drain region and a shallow trench isolation. A silicide is then formed over a landed area of the source/drain region but is blocked by the blocking layer from forming over the junction between the source/drain region and the shallow trench isolation. This prevents device leakage at this location.

摘要翻译： 一种防止设备泄漏的方法和结构。 该方法和结构包括在源极/漏极区域和浅沟槽隔离之间的结上形成优选氮化物的阻挡层。 然后在源极/漏极区域的着陆区域上形成硅化物，但是被阻挡层阻挡在源极/漏极区域和浅沟槽隔离之间的结上形成。 这可以防止在此位置的设备泄漏。

公开(公告)号：US06194702B1

公开(公告)日：2001-02-27

申请号：US09290755

申请日：1999-04-13

申请人： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

发明人： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

IPC分类号： H01L3100

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/0352

摘要： The present invention is a complementary active pixel sensor cell and method of making and using the same. The complementary active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a complementary active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and complementary PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

摘要翻译： 本发明是补充有源像素传感器单元及其制造和使用方法。 补充有源像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用在互补的有源像素传感器单元电路中照射光子产生的空穴。 创建两个有源像素传感器单元电路，NFET电路和互补PFET电路用于光电二极管。 NFET电路捕获电子电流。 PFET电路捕获空穴电流。 电流的总和大约是使用类似尺寸的光电二极管区域的传统有源像素传感器电路的总和的两倍。