公开(公告)号：US5392401A

公开(公告)日：1995-02-21

申请号：US5425

申请日：1993-01-21

申请人： Gerard Barucchi ,  Jean Calvignac ,  Daniel Orsatti ,  Andre Tracol

发明人： Gerard Barucchi ,  Jean Calvignac ,  Daniel Orsatti ,  Andre Tracol

IPC分类号： G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F15/17375

摘要： The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.

摘要翻译： 该系统在包括从N个数据处理单元（8）中选择的原始单元和目标单元的单元对之间执行数据分组的优化数量的同时传送。 每个数据处理单元包括一组出站队列，其中一个出站队列与其可以发送数据分组的数据处理单元中的每一个相关联，用于存储要由数据处理单元发送到数据处理单元的数据分组 有一个出站队列。 响应于在先前的突发期间由调度器4产生的控制信号，在数据交换机6的时间突发Ti + 1的控制下，在由线路16-1至16-N上的单元发送到数据交换的切换控制信号的情况下， 时间Ti 调度器运行选择算法，其给出每个单位在给定时间段内作为原始单位的相等概率。

公开(公告)号：US5333269A

公开(公告)日：1994-07-26

申请号：US965554

申请日：1992-10-23

申请人： Jean Calvignac ,  Jean-Pierre Lips ,  Jean-Marc Millet ,  Jean-Marie Munier ,  Bernard Naudin

发明人： Jean Calvignac ,  Jean-Pierre Lips ,  Jean-Marc Millet ,  Jean-Marie Munier ,  Bernard Naudin

IPC分类号： G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177 ,  H04L12/40

CPC分类号： G06F15/167 ,  G06F9/544

摘要： A device for interconnecting source users and destination users includes a common bus to which a memory with a plurality of independent buffers, a memory interface (22) and a central control apparatus (26) are connected. The memory interface (22) receives messages from source users, stores the messages in selected buffers and chains the buffers together. The central control apparatus generates inbound message queues and outbound message queues in response to commands which it receives from the memory interface.

摘要翻译： 用于互连源用户和目的用户的设备包括公共总线，具有多个独立缓冲器的存储器，存储器接口（22）和中央控制设备（26）连接到该总线。 存储器接口（22）从源用户接收消息，将消息存储在所选择的缓冲器中并将缓冲器链接在一起。 中央控制装置响应于从存储器接口接收到的命令，生成入站消息队列和出站消息队列。

公开(公告)号：US5237572A

公开(公告)日：1993-08-17

申请号：US830128

申请日：1992-01-31

申请人： Mohamed Badaoui ,  Jean Calvignac ,  Guy Carle ,  Christian Garcia ,  Pierre Vachee

发明人： Mohamed Badaoui ,  Jean Calvignac ,  Guy Carle ,  Christian Garcia ,  Pierre Vachee

IPC分类号： G06F13/38

CPC分类号： G06F13/385

摘要： An Active Remote Module (ARM) attaches end user devices to any port of a multiport communications processing unit. The ARM includes circuit arrangements which receive serial streams of data and clock information which are arranged into data slots, control slots and outband slot carrying characteristic information, including ARM address, ARM type, end user data rate, etc., about the ARM and the end user devices. By issuing selective commands, a line adapter in the multiport communications processing unit is made aware of the user devices connected to its port and structure the data to meet the requirement of the attached end user devices.

摘要翻译： 主动远程模块（ARM）将终端用户设备连接到多端口通信处理单元的任何端口。 ARM包括电路布置，其接收串行数据流和时钟信息，这些数据和时钟信息被布置成关于ARM和ARM的数据时隙，控制时隙和携带特征信息的带外特征信息，包括ARM地址，ARM类型，最终用户数据速率等 最终用户设备。 通过发出选择性命令，使多端口通信处理单元中的线路适配器知道连接到其端口的用户设备并且构造数据以满足所附连接的终端用户设备的要求。

公开(公告)号：US4819230A

公开(公告)日：1989-04-04

申请号：US77485

申请日：1987-07-24

申请人： Jean Calvignac ,  Pierre Secondo

发明人： Jean Calvignac ,  Pierre Secondo

IPC分类号： H04Q11/04 ,  H04L12/64 ,  H04M11/00 ,  H04J3/26

CPC分类号： H04L12/64

摘要： The invention relates to a mechanism to be used in an integrated packet/circuit switched telecommunication network. It allows instantaneously on a per slot basis, the re-allocation of unused bandwidth left by a circuit user source to the background packet flow, and allows giving it back to the circuit source as it resumes its activity. The circuit user data Cd are sent through the network during slots of frames which are assigned to the circuit users on a per- call basis. Interfacing means (30, 32) are provided to generate slot qualifying bits Caq which are set to a first value when the corresponding circuit users are active and to a second value when the corresponding cirucit users are inactive. These qualifying bits are transported through the network in correspondence with the slot they qualify and sensed to cause the slots having a Caq set to the second value to be filled with packet bits.

公开(公告)号：US4493051A

公开(公告)日：1985-01-08

申请号：US433609

申请日：1982-10-12

申请人： Bernard Brezzo ,  Jean Calvignac ,  Richard Dambricourt ,  Andre Masclet ,  Jean-Pierre Sanche

发明人： Bernard Brezzo ,  Jean Calvignac ,  Richard Dambricourt ,  Andre Masclet ,  Jean-Pierre Sanche

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/38 ,  G06F3/04

CPC分类号： G06F13/385

摘要： A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line. These stores are addressed by a control and address unit which includes first and second address counters under the control of an elementary time counter, the first counter outputting the address information relating to the first store during time t provided for scanning a line, and the second counter outputting the address information relative to the second store during time nt, n being at least equal to 4, and control circuitry receiving said address information and the elementary time information for providing at the outputs of the control and address unit, memory address and read/write control information at times selected during the scanning period and sequentially, the addresses of the present lines which are scanned.

摘要翻译： 在连接到控制存储器的控制存储器的控制下操作的行扫描装置，其中存储器位置区域被分配给每一行，用于通信控制器中的线路适配器，用于从或从终端接收或发送消息位 使用任何协议连接到线路。 它包括第一存储器，其包括第一存储器和第二存储器，被分配给可以在同一时间读取和写入的每个存储器中的每一行的区域以及包括单个存储器的第二存储器，其中存储位置 区域被分配到每一行。 这些存储器由控制和地址单元寻址，该控制和地址单元在基本时间计数器的控制下包括第一和第二地址计数器，第一计数器在时间t内输出与第一存储有关的地址信息用于扫描行， 计数器在时间nt，n至少等于4时输出相对于第二存储器的地址信息，以及控制电路，其接收所述地址信息和用于在控制和地址单元的输出处提供存储器地址和读取的基本时间信息 在扫描期间选择的时间顺序地写入控制信息，扫描的当前行的地址。

公开(公告)号：US20080013541A1

公开(公告)日：2008-01-17

申请号：US11776807

申请日：2007-07-12

申请人： Jean Calvignac ,  Gordon Davis

发明人： Jean Calvignac ,  Gordon Davis

IPC分类号： H04L12/54

CPC分类号： H04L49/602 ,  H04L49/354 ,  H04L49/604 ,  H04L69/22

摘要： A method and structure are disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiples of such dispatch messages are bundled into a single composite dispatch message. Thus, selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.

摘要翻译： 公开了一种用于将适当数据发送到网络处理系统的方法和结构，所述网络处理系统包括用于提取网络处理器使用的协议头域的改进技术。 该技术包括根据分组中存在的协议报头的类型对分组的基本分类。 根据分类结果，从相应的标题中提取特定参数字段。 来自分组中的一个或多个协议报头的所有这些参数字段被连接成压缩的调度消息。 这种分派消息的倍数被捆绑成单个复合调度消息。 因此，来自N个分组的选择的报头字段以单个复合调度消息传递到网络处理器，从而将网络处理器的分组转发能力提高N倍。同样地，多个入队消息被捆绑到单个复合入口消息中以引导入队 并且对N个分组的束进行帧改变。

公开(公告)号：US06996650B2

公开(公告)日：2006-02-07

申请号：US10147682

申请日：2002-05-16

申请人： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

发明人： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

IPC分类号： G06F13/42 ,  G06F13/14 ,  G06F13/40

CPC分类号： G06F13/4273 ,  G06F13/4059

摘要： A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

摘要翻译： 提供了一种用于实现点对点总线的多个可配置子总线的方法和装置。 多个总线互连中的每一个包括连接到点对点总线的发送接口和接收接口。 每个发送接口包括耦合在缓冲器和点到点总线之间的发送缓冲器和串行器。 发送缓冲区提供发送源和串行器之间的异步接口。 串行器以第一频率从发送缓冲器接收数据和控制信号，并以更高的第二频率在点对点总线上发送数据和控制信号。 发射导向逻辑耦合在多个总线互连的发射源和每个发射缓冲器之间。 发射导向逻辑基于所选择的总线配置将数据和控制信号从发射源引导到每个所选发射缓冲器中的一个。

公开(公告)号：US5572697A

公开(公告)日：1996-11-05

申请号：US992314

申请日：1992-12-21

申请人： Denis Chevalier ,  Jean Calvignac ,  Jean-Marie Munier ,  Bernard Naudin ,  Maurice Duault

发明人： Denis Chevalier ,  Jean Calvignac ,  Jean-Marie Munier ,  Bernard Naudin ,  Maurice Duault

IPC分类号： G06F11/00 ,  G06F5/06 ,  G06F13/00 ,  G06F15/167

CPC分类号： G06F15/167 ,  G06F5/06 ,  G06F2205/064

摘要： Apparatus for recovering lost buffer contents in a data processing system uses a memory divided into a plurality of buffers provided with buffer control blocks, through which source and destination users exchange information. A buffer management circuit is responsive to requests from users for allocating buffers to source users in order that source users may store the information to be sent to the destination users. This circuit builds buffer queues and dequeues buffers from the queues to send the information contained therein to the destination users and releases the buffers afterwards. A time mark register is settable to n different values in a predetermined order. The value of the time mark register is changed at the expiration of a time period P. Each time a buffer is allocated to one user, the current value of the time mark register is written into a time mark field of the buffer control block and a state field is set to a first value (leased). When the buffer is released, the state field is set to a second value (released). The contents of the buffer control blocks are read at regular time intervals t after period P, and the state field of every buffer control block is tested to determine whether it is set to the second value. If not so set, the time mark field is compared with the value the time mark register had at the time t-xP, where x is a number such as 1

摘要翻译： 用于恢复数据处理系统中的丢失缓冲器内容的装置使用分配有缓冲器控制块的多个缓冲器的存储器，源和目的地用户通过该缓冲器控制块交换信息。 缓冲器管理电路响应于用户向源用户分配缓冲区的请求，以便源用户可以存储要发送到目的地用户的信息。 此电路构建缓冲区队列，并从队列中将缓冲区从队列中出发，将其中包含的信息发送到目标用户，然后释放缓冲区。 时间标记寄存器可按预定顺序设置为n个不同的值。 时间标记寄存器的值在时间段P的期满时被改变。每当向一个用户分配缓冲器时，时间标记寄存器的当前值被写入缓冲器控制块的时间标记字段，并且 状态字段设置为第一个值（租用）。 当释放缓冲区时，状态字段被设置为第二个值（已释放）。 在周期P之后以规则的时间间隔t读取缓冲器控制块的内容，并且测试每个缓冲器控制块的状态字段以确定其是否被设置为第二值。 如果不设置，则时间标记字段与时间标记寄存器在时间t-xP处具有的值进行比较，其中x是诸如1

公开(公告)号：US5557608A

公开(公告)日：1996-09-17

申请号：US446997

申请日：1995-05-22

申请人： Jean Calvignac ,  Claude Galand ,  Didier Giroir ,  Gerald Lebizay ,  Daniel Mauduit ,  Victor Spagnol

发明人： Jean Calvignac ,  Claude Galand ,  Didier Giroir ,  Gerald Lebizay ,  Daniel Mauduit ,  Victor Spagnol

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L47/56 ,  H04L12/5693 ,  H04L29/06 ,  H04L47/245 ,  H04L47/6215 ,  H04L47/623 ,  H04L47/6255 ,  H04L47/627 ,  H04L49/9057 ,  H04L69/324

摘要： In a packet switched communications system an incoming real-time packet is imbedded after the next block of data of the non-real-time packet being transmitted. This object is accomplished by transmitting each packet along with at least a 1-byte trailer which is used to indicate the packet type, whether the current block of non real time data is preempted or whether the current block of non real time data is resumed.

摘要翻译： 在分组交换通信系统中，在正在发送的非实时分组的下一个数据块之后嵌入传入的实时分组。 该目的是通过发送每个分组以及至少一个用于指示分组类型的1字节预告片，无论当前的非实时数据块是抢占还是当前的非实时数据块都被恢复。

公开(公告)号：US5134636A

公开(公告)日：1992-07-28

申请号：US657906

申请日：1991-02-20

申请人： Gerard Barucchi ,  Jean Calvignac ,  Jose Galcera ,  Gilles Toubol ,  Andre Tracol ,  Daniel Orsatti

发明人： Gerard Barucchi ,  Jean Calvignac ,  Jose Galcera ,  Gilles Toubol ,  Andre Tracol ,  Daniel Orsatti

IPC分类号： G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0629

摘要： The synchronization circuit resynchronizes the data bits received from remote devices on line or link (20-1) with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in an n-bit cyclic buffer (114-1) with the received bit clock CS. The arranged bits are sequentially picked at the opposite buffer position with the central clock CO. The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.