公开(公告)号：US09871032B2

公开(公告)日：2018-01-16

申请号：US14848364

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0266 ,  H01L27/0274 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7835

Abstract: A gate-grounded metal oxide semiconductor (GGMOS) device is disclosed. The GGMOS is an n-type (GGNMOS) transistor used as an electrostatic discharge (ESD) protection device. The GGMOS includes a base extension region under an elevated source. The elevated source and base extension regions increase Leff and reduce beta, increasing performance of the ESD protection.

公开(公告)号：US09818867B2

公开(公告)日：2017-11-14

申请号：US14522606

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng Jason Tan ,  Yuan Sun ,  Eng Huat Toh ,  Ying Keung Leung ,  Kiok Boone Elgin Quek

IPC: H01L27/115 ,  H01L29/78 ,  H01L49/02 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11558 ,  G11C16/04 ,  H01L29/94

CPC classification number: H01L29/7835 ,  G11C16/0433 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/94

Abstract: Non-volatile (NV) Multi-time programmable (MTP) memory cells are presented. The memory cell includes a substrate and first and second wells in the substrate. The memory cell includes first transistor having a select gate, second transistor having a floating gate adjacent to one another and on the second well, and third transistor having a control gate on the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and second wells. The transistors include first and second diffusion regions disposed adjacent to sides of the gates. The first and second diffusion regions include base lightly doped drain (LDD) and halo regions. One of the first and second diffusion regions of one of the second and third transistors includes second LDD and halo regions having higher dopant concentrations than the base LDD and halo regions.

公开(公告)号：US09754939B2

公开(公告)日：2017-09-05

申请号：US14938499

申请日：2015-11-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/66537 ,  H01L29/66803

Abstract: Integrated circuits including multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes providing a semiconductor fin structure overlying a semiconductor substrate. The semiconductor fin structure has a first sidewall, a second sidewall opposite the first sidewall, and an upper surface. The method includes forming a first gate along the first sidewall of the semiconductor fin structure with a first threshold voltage. Further, the method includes forming a second gate along the second sidewall of the semiconductor fin structure with a second threshold voltage different from the first threshold voltage.

公开(公告)号：US09653365B1

公开(公告)日：2017-05-16

申请号：US15093888

申请日：2016-04-08

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Khee Yong Lim ,  Jae Han Cha ,  Chia Ching Yeo ,  Kiok Boone Elgin Quek

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L21/84 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/1207

Abstract: A method for fabricating an integrated circuit that include providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate, dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and one or both of a medium voltage FET region and a high voltage FET regions, and forming a low voltage FET within the low voltage FET regions and forming a medium and/or high voltage FET within the medium and/or high voltage FET region(s). Channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer that is disposed above a buried oxide layer of the ETSOI substrate, whereas channel, source, and drain structures of the medium and/or high voltage FETs are formed at least partially below the upper silicon layer.

公开(公告)号：US09646963B1

公开(公告)日：2017-05-09

申请号：US15181446

申请日：2016-06-14

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Yuan Sun ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02 ,  H01L21/8234

CPC classification number: H01L29/94 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0688 ,  H01L29/66189

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.