公开(公告)号：US06653675B2

公开(公告)日：2003-11-25

申请号：US09879604

申请日：2001-06-12

申请人： Fernando Gonzalez ,  Roger Lee

发明人： Fernando Gonzalez ,  Roger Lee

IPC分类号： H01L27108

CPC分类号： H01L21/823462 ,  H01L27/10873 ,  H01L27/10894

摘要： Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region comprises a harder material, specifically silicon nitride, and has a lesser overall equivalent oxide thickness. The illustrated peripheral gate dielectric has an oxide-nitride-oxide construction. The disclosed process includes forming silicon nitride over the entire chip followed by selectively etching off the silicon nitride from the memory array region, without requiring a separate mask as compared to conventional processes. After the selective etch, oxide is grown over the entire chip, growing differentially thicker in the memory array region.

摘要翻译： 公开了用于集成电路上的不同区域的双栅介质结构及其方法。 在所示实施例中，芯片的存储器阵列区域中的栅极电介质由氧化硅形成，而外围区域中的栅极电介质包含更硬的材料，特别是氮化硅，并且具有较小的总的等效氧化物厚度。 所示的外围栅极电介质具有氧化物 - 氧化物 - 氧化物结构。 所公开的方法包括在整个芯片上形成氮化硅，随后与存储器阵列区域选择性地蚀刻掉氮化硅，而不需要与常规工艺相比分开的掩模。 在选择性蚀刻之后，氧化物在整个芯片上生长，在存储器阵列区域中生长差异较大。

公开(公告)号：US6137133A

公开(公告)日：2000-10-24

申请号：US76327

申请日：1998-05-11

申请人： Ralph Kauffman ,  Roger Lee

发明人： Ralph Kauffman ,  Roger Lee

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming a non-volatile memory array includes, a) providing first and second floating gate word lines atop a semiconductor substrate, the first and second word lines being adjacent one another and defining transistor active area therebetween, the first and second word lines having inwardly opposing and facing active area sidewall edges, the first and second word lines each comprising respective nitride capping layers having a thickness of at least about 1000 Angstroms; b) providing a nitride spacer layer over the nitride capping layer; c) anisotropically etching the nitride spacer layer to produce insulating sidewall spacers over the first and second word line active area sidewall edges, the anisotropic etching leaving at least a portion of the nitride capping layer covering each of the first and second word lines, the portion of each nitride capping layer joining with one of the sidewall spacers to cover the first and second word line active area sidewall edges and thereby defining a widened mask misalignment area than were such capping layer portions not present; d) providing an oxide layer over the sidewall spacers and capping layer; e) patterning and etching the oxide layer selectively relative to the nitride capping layer and sidewall spacers to define a contact opening to the active area, the contact opening overlapping with at least one nitride capping layer portion on one of the word lines; and f) providing an electrically conductive plug within the contact opening. A non-volatile memory array is disclosed.

摘要翻译： 一种形成非易失性存储器阵列的方法包括：a）在半导体衬底顶部提供第一和第二浮栅字线，第一和第二字线彼此相邻并且在其间限定晶体管有源区，第一和第二字线 具有向内相对并面对有效区域侧壁边缘，所述第一和第二字线各自包括具有至少约1000埃厚度的相应的氮化物覆盖层; b）在氮化物覆盖层上方提供氮化物间隔层; c）各向异性蚀刻所述氮化物间隔层以在所述第一和第二字线有源区侧壁边缘上方产生绝缘侧壁间隔物，所述各向异性蚀刻留下覆盖所述第一和第二字线中的每一个的所述氮化物覆盖层的至少一部分， 每个氮化物覆盖层与一个侧壁间隔物接合以覆盖第一和第二字线有源区域侧壁边缘，从而限定比不存在的封盖层部分更宽的掩模未对准面积; d）在所述侧壁间隔物和覆盖层上方提供氧化物层; e）相对于氮化物覆盖层和侧壁间隔物选择性地图案化和蚀刻氧化物层以限定到有源区域的接触开口，接触开口与一条字线上的至少一个氮化物覆盖层部分重叠; 以及f）在所述接触开口内提供导电插头。 公开了一种非易失性存储器阵列。

公开(公告)号：US6117728A

公开(公告)日：2000-09-12

申请号：US56391

申请日：1998-04-06

申请人： Ralph Kauffman ,  Roger Lee

发明人： Ralph Kauffman ,  Roger Lee

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming a non-volatile memory array includes, a) providing first and second floating gate word lines atop a semiconductor substrate, the first and second word lines being adjacent one another and defining transistor active area therebetween, the first and second word lines having inwardly opposing and facing active area sidewall edges, the first and second word lines each comprising respective nitride capping layers having a thickness of at least about 1000 Angstroms; b) providing a nitride spacer layer over the nitride capping layer; c) anisotropically etching the nitride spacer layer to produce insulating sidewall spacers over the first and second word line active area sidewall edges, the anisotropic etching leaving at least a portion of the nitride capping layer covering each of the first and second word lines, the portion of each nitride capping layer joining with one of the sidewall spacers to cover the first and second word line active area sidewall edges and thereby defining a widened mask misalignment area than were such capping layer portions not present; d) providing an oxide layer over the sidewall spacers and capping layer; e) patterning and etching the oxide layer selectively relative to the nitride capping layer and sidewall spacers to define a contact opening to the active area, the contact opening overlapping with at least one nitride capping layer portion on one of the word lines; and f) providing an electrically conductive plug within the contact opening. A non-volatile memory array is disclosed.

公开(公告)号：US6087221A

公开(公告)日：2000-07-11

申请号：US917029

申请日：1997-08-22

申请人： Gregg Rettschlag ,  Roger Lee

发明人： Gregg Rettschlag ,  Roger Lee

IPC分类号： H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/11536

摘要： A method for fabricating dissimilar devices in an integrated circuit. In one embodiment, the method can be used to fabricate flash memory, including MOS transistors and flash cells. The method can be used to substantially cofabricate the MOS transistors and flash cells, particularly their gates. The method includes forming layers of adjacent materials for the MOS transistor gates and the flash cell gates, and simultaneously forming the MOS transistor gates and the flash cell gates from the layers of adjacent materials. The method further includes defining drains of the flash cells separate from defining sources of the flash cells.

摘要翻译： 一种用于在集成电路中制造不同器件的方法。 在一个实施例中，该方法可用于制造闪存，包括MOS晶体管和闪存单元。 该方法可用于基本上共同制造MOS晶体管和闪存单元，特别是其栅极。 该方法包括为MOS晶体管栅极和闪存单元栅极形成相邻材料的层，并且从相邻材料层同时形成MOS晶体管栅极和闪存单元栅极。 该方法还包括定义闪存单元的漏极与闪光单元的定义源分开。

公开(公告)号：USD407074S

公开(公告)日：1999-03-23

申请号：US74866

申请日：1997-08-11

申请人： Roger Lee

设计人： Roger Lee

公开(公告)号：US5780891A

公开(公告)日：1998-07-14

申请号：US634118

申请日：1996-04-17

申请人： Ralph Kauffman ,  Roger Lee

发明人： Ralph Kauffman ,  Roger Lee

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/34

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/511 ,  Y10S438/954

摘要： A floating memory device utilizing a composite oxide/oxynitride or oxide/oxynitride/oxide interpoly dielectric.

摘要翻译： 利用复合氧化物/氧氮化物或氧化物/氧氮化物/氧化物层间电介质的浮动存储器件。

公开(公告)号：US5342288A

公开(公告)日：1994-08-30

申请号：US924193

申请日：1992-08-03

申请人： Roger Lee ,  Paul Martin

发明人： Roger Lee ,  Paul Martin

IPC分类号： A61F5/058 ,  A61F5/00

CPC分类号： A61F5/0585

摘要： A traction splint for a long bone extremity fracture in which the length of the frame of the traction splint and the angle of the ischial pad of the traction splint relative to the frame are adjusted simultaneously. The ischial pad is pivotally connected to the frame and the pivotal movement of the ischial pad relative to the frame is restricted or limited up to 35.degree..

摘要翻译： 用于长骨肢骨折的牵引夹板，其中牵引夹板的框架的长度和牵引夹板的坐标垫相对于框架的角度被同时调整。 坐骨垫可枢转地连接到框架上，坐骨垫相对于框架的枢转运动被限制或限制在35度。