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81.发明授权Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求以固定的时间表被服务公开(公告)号：US07447844B2
公开(公告)日：2008-11-04
申请号：US11457322
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译： 处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录。 缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑 其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。 调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。
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82.发明授权Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction 失效用于使用基于历史的预测来预测性地选择操作的广播范围的数据处理系统和方法公开(公告)号：US07444494B2
公开(公告)日：2008-10-28
申请号：US11140821
申请日：2005-05-31
申请人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
CPC分类号： G06F12/0833 , G06F2212/507
摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.
摘要翻译： 根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。 通过参考预测器预测性地选择后续操作的广播范围。
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83.发明申请REDUCING NUMBER OF REJECTED SNOOP REQUESTS BY EXTENDING TIME TO RESPOND TO SNOOP REQUEST 审中-公开通过延长时间减少违反SNOOP要求的数量以应对SNOOP要求公开(公告)号：US20080201534A1
公开(公告)日：2008-08-21
申请号：US12114786
申请日：2008-05-04
IPC分类号： G06F12/08
CPC分类号： G06F13/1605 , G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.
摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 监听请求被输入到停止/重新排序单元的第一可用锁存器中，除非停止/重新排序单元已满，在这种情况下，新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。 侦听请求具有比来自处理器的请求更高的优先级，并且仲裁机制通过处理器请求选择侦听请求，除非仲裁机制另请求（“停止请求”）到停止/重新排序单元。 通过具有比处理器请求更高优先级的侦听请求，减少了被拒绝的侦听请求的数量。 通过使仲裁机制发出停顿请求，处理器不会饿死。
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84.发明授权Cache memory, processing unit, data processing system and method for filtering snooped operations 有权缓存存储器，处理单元，数据处理系统和过滤窥探操作的方法公开(公告)号：US07404046B2
公开(公告)日：2008-07-22
申请号：US11055418
申请日：2005-02-10
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.
摘要翻译： 高速缓存一致数据处理系统至少包括支持第一处理单元的第一高速缓冲存储器和支持第二处理单元的第二高速缓冲存储器。 第一缓存存储器包括缓存阵列和高速缓存阵列的内容的高速缓存目录。 响应于第一高速缓冲存储器在互连上检测指定请求地址的广播操作，第一高速缓冲存储器从操作中确定与请求地址相关联的操作类型和一致性状态。 响应于确定类型和一致性状态，第一高速缓存存储器过滤掉广播操作而不访问高速缓存目录。
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85.发明授权Reducing number of rejected snoop requests by extending time to respond to snoop request 失效通过延长响应窥探请求的时间来减少被拒绝的窥探请求数公开(公告)号：US07386681B2
公开(公告)日：2008-06-10
申请号：US11056679
申请日：2005-02-11
IPC分类号： G06F12/00
CPC分类号： G06F13/1605 , G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.
摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 监听请求被输入到停止/重新排序单元的第一可用锁存器中，除非停止/重新排序单元已满，在这种情况下，新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。 侦听请求具有比来自处理器的请求更高的优先级，并且仲裁机制通过处理器请求选择侦听请求，除非仲裁机制另请求（“停止请求”）到停止/重新排序单元。 通过具有比处理器请求更高优先级的侦听请求，减少了被拒绝的侦听请求的数量。 通过使仲裁机制发出停顿请求，处理器不会饿死。
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86.发明申请Processor, Data Processing System and Method Supporting Improved Coherency Management of Castouts 有权处理器，数据处理系统和方法支持改进的Castouts的一致性管理公开(公告)号：US20080071994A1
公开(公告)日：2008-03-20
申请号：US11532981
申请日：2006-09-19
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815
摘要： According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.
摘要翻译： 根据一个实施例，一种数据处理系统中的一致性管理方法包括：将高速缓存行以独占所有权一致性状态保存在上级高速缓冲存储器中，之后从高级缓存存储器中移除高速缓存行， 从高级缓存存储器到高级缓存的高速缓存行。 丢弃请求包括共享所有权一致性状态的指示。 响应于抛出请求，高速缓存行以根据转储请求确定的一致性状态被放置在较低级高速缓冲存储器中。
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87.发明申请Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced by State Machines with Differing Functionality 失效数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务公开(公告)号：US20080016279A1
公开(公告)日：2008-01-17
申请号：US11457333
申请日：2006-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译： 数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。 多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求， 它能够维修。
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88.发明申请DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING CONTROLLABLE STORE GATHER WINDOWS 审中-公开数据处理系统，具有可控储存窗口的数据处理的处理器和方法公开(公告)号：US20070288694A1
公开(公告)日：2007-12-13
申请号：US11423717
申请日：2006-06-13
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/3834
摘要： A data processing system includes a processor core and a memory subsystem coupled to the processor core. The memory subsystem includes data storage and a store queue including a plurality of entries for buffering store operations to be performed with reference to the data storage. The memory subsystem further includes a store queue controller that gathers multiple store requests received from the processor core into a single store operation buffered within an entry of the store queue. The store queue controller applies store gathering windows of differing durations to differing ones of the plurality of entries in response to control information received from the processor core.
摘要翻译： 数据处理系统包括处理器核心和耦合到处理器核心的存储器子系统。 存储器子系统包括数据存储器和存储队列，其包括用于缓冲要参考数据存储器执行的存储操作的多个条目。 存储器子系统还包括存储队列控制器，其将从处理器核心接收的多个存储请求收集到缓冲在存储队列的条目内的单个存储操作中。 存储队列控制器响应于从处理器核心接收到的控制信息，将具有不同持续时间的商店收集窗口应用到多个条目中的不同条目。
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公开(公告)号：US08453080B2
公开(公告)日：2013-05-28
申请号：US12335766
申请日：2008-12-16
CPC分类号： G06F17/5045
摘要： One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.
摘要翻译： 一个或多个硬件描述语言（HDL）文件描述了定义要仿真的数字设计的多个分层布置的设计实体以及不属于数字设计的多个配置实体，所述多个配置实体逻辑地控制数字的多个配置锁存器的设置 设计。 编译HDL文件以获得数字设计的模拟可执行模型和相关联的配置数据库。 编译包括解析配置语句，该配置语句指定配置实体的实例与指定的配置锁存器之间的关联，确定在HDL文件中是否描述了指定的配置锁存器，以及如果不是，则创建指示 配置数据库，配置锁存器的实例与其无法绑定到的配置锁存器具有指定的关联。
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公开(公告)号：US08108199B2
公开(公告)日：2012-01-31
申请号：US12130104
申请日：2008-05-30
申请人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F9/45
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.
摘要翻译： 根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型 在一个或多个设计实体的实例内的一个或多个仪表实体。 然后使用仪器化模拟可执行模型对设计的操作进行模拟。 模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑 聚合相位信号表示特定相位的出现。
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