公开(公告)号：US08163605B2

公开(公告)日：2012-04-24

申请号：US12704004

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66666

摘要： It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be obtained. The method comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a dummy gate dielectric film and a dummy gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a first dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode, through a gate dielectric film; forming a first dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on each of the second-conductive-type semiconductor layers formed in the upper portion of and underneath the pillar-shaped first-conductive-type semiconductor layer; removing the dummy gate dielectric film and the dummy gate electrode and forming a high-k gate dielectric film and a metal gate electrode.

摘要翻译： 旨在提供一种能够获得用于降低源极，漏极和栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及要获得的柱状半导体的期望直径的结构的SGT制造方法。 该方法包括以下步骤：形成柱状第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极电极的顶部接触的第一电介质膜，通过栅极电介质膜形成; 在所述栅电极的侧壁上形成第一电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层的上部和下方的每个第二导电型半导体层上形成金属 - 半导体化合物; 去除伪栅极电介质膜和伪栅电极并形成高k栅极电介质膜和金属栅电极。

公开(公告)号：US20110303973A1

公开(公告)日：2011-12-15

申请号：US13116506

申请日：2011-05-26

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  King-Jien Chui ,  Yisuo Li ,  Yu Jiang ,  Xiang Li ,  Zhixian Chen ,  Nansheng Shen ,  Vladimir Bliznetsov ,  Kavitha Devi Buddharaju ,  Navab Singh

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  King-Jien Chui ,  Yisuo Li ,  Yu Jiang ,  Xiang Li ,  Zhixian Chen ,  Nansheng Shen ,  Vladimir Bliznetsov ,  Kavitha Devi Buddharaju ,  Navab Singh

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42392 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.

摘要翻译： 根据本发明的半导体器件是nMOS SGT，并且由第一n +型硅层，含有金属的第一栅电极和第二n +型硅层构成，所述第二n +型硅层布置在垂直定位在第一n +型硅层上的第一柱状硅层的表面上 第一平面硅层。 此外，第一绝缘膜位于第一栅电极和第一平面硅层之间，第二绝缘膜位于第一栅电极的顶表面上。 此外，含有第一栅电极的金属被第一n +型硅层，第二n +型硅层，第一绝缘膜和第二绝缘膜包围。

公开(公告)号：US07919990B2

公开(公告)日：2011-04-05

申请号：US12697683

申请日：2010-02-01

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H03K19/20 ,  H03K19/094 ,  H01L23/52

CPC分类号： H01L27/092 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/84 ,  H01L29/78642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the present invention comprises an SGT based, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A first CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 1st column and an intersection of the 2nd row and the 1st column, and an nMOS SGT arranged at an intersection of the 1st row and the 2nd column. A second CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 3rd column and an intersection of the 2nd row and the 3rd column, and an nMOS SGT arranged at an intersection of the 2nd row and the 2nd column.

摘要翻译： 本发明的半导体器件包括基于SGT的至少两级CMOS反相器级联电路，其被配置为允许pMOS SGT具有比nMOS SGT的栅极宽大两倍的栅极宽度。 第一CMOS反相器包括布置在第一行和第一列的相交处的两个pMOS SGT和第二行和第一列的交点以及布置在第一行和第二列的交点处的nMOS SGT 柱。 第二CMOS反相器包括布置在第一行和第三列的相交处的两个pMOS SGT和第二行和第三列的交集，以及布置在第二行和第二列的交点处的nMOS SGT 柱。

公开(公告)号：US20100219464A1

公开(公告)日：2010-09-02

申请号：US12703991

申请日：2010-02-11

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/458 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642

摘要： Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 公开了一种半导体器件制造方法，其包括以下步骤：在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在所述柱状的第一导电型半导体层周围形成具有金属膜和非晶硅或多晶硅膜的叠层结构的栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成第一和第二侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成金属 - 半导体化合物; 在栅电极上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成接触; 并且在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成接触。

公开(公告)号：US20100219457A1

公开(公告)日：2010-09-02

申请号：US12700315

申请日：2010-02-04

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L31/14 ,  H01L31/18 ,  H01L31/0352

CPC分类号： H01L27/14607 ,  H01L27/14614 ,  H01L27/14643

摘要： It is an object to provide an image sensor having a sufficiently-large ratio of a surface area of a light-receiving section to an overall surface area of one pixel. This object is achieved by a solid-state imaging device comprising: a signal line formed on a substrate; an island-shaped semiconductor arranged on the signal line; and a pixel selection line connected to a top of the island-shaped semiconductor, wherein the island-shaped semiconductor includes: a first semiconductor layer formed as a bottom portion of the island-shaped semiconductor and connected to the signal line; a second semiconductor layer formed above and adjacent to the first semiconductor layer; a gate connected to the second semiconductor layer through a dielectric film; a charge storage section comprised of a third semiconductor layer connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein; and a fourth semiconductor layer formed above and adjacent to the second and third semiconductor layers, and wherein the pixel selection line is comprised of a transparent conductive film, and a part of the gate is disposed inside a depression formed in a sidewall of the second semiconductor layer.

摘要翻译： 本发明的目的是提供一种具有足够大的光接收部分的表面积与一个像素的整个表面积之比的足够大的图像传感器。 该目的通过一种固态成像装置实现，该固态成像装置包括：形成在基板上的信号线; 布置在信号线上的岛状半导体; 以及连接到岛状半导体的顶部的像素选择线，其中所述岛状半导体包括：形成为所述岛状半导体的底部并连接到所述信号线的第一半导体层; 形成在第一半导体层上方并与其相邻的第二半导体层; 通过电介质膜与第二半导体层连接的栅极; 电荷存储部，包括连接到第二半导体层并且响应于接收光而适应于其中的电荷量的变化的第三半导体层; 以及第四半导体层，其形成在第二和第三半导体层的上方并与其相邻，并且其中像素选择线由透明导电膜构成，并且栅极的一部分设置在形成在第二半导体的侧壁中的凹陷内 层。

公开(公告)号：US20100207199A1

公开(公告)日：2010-08-19

申请号：US12704000

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L21/66

CPC分类号： H01L29/78642 ,  H01L22/26

摘要： The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 该方法包括以下步骤：在形成在基板上的氧化膜上形成平面半导体层，然后在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在柱状的第一导电型半导体层周围形成栅极电介质膜和由金属制成的栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层。

公开(公告)号：US20100187600A1

公开(公告)日：2010-07-29

申请号：US12699611

申请日：2010-02-03

申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

公开(公告)号：US07713805B2

公开(公告)日：2010-05-11

申请号：US11976217

申请日：2007-10-23

申请人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

发明人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66068

摘要： A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film and an edge portion of the gate electrode is rounded and oxidized.

摘要翻译： 制造具有MOS结构的碳化硅半导体器件的方法包括制备由碳化硅制成的衬底，并形成沟道区，第一杂质区，第二杂质区，栅绝缘层和栅电极，以形成 半导体元件。 此外，在半导体元件上形成膜以提供层间绝缘层的材料，并且在湿气氛中在约700℃或更高的温度下进行回流工艺，使得层间绝缘层由 该膜和栅电极的边缘部分被圆化并氧化。

公开(公告)号：US20100102362A1

公开(公告)日：2010-04-29

申请号：US12603001

申请日：2009-10-21

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L31/14 ,  H01L31/18

CPC分类号： H01L27/14812 ,  H01L29/768

摘要： It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel. The solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion, a first-conductive type high-concentration impurity-doped element isolation region formed in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region, a second-conductive type photoelectric conversion region formed beneath the first-conductive type high-concentration impurity region and in a part of a lower region of the remaining part of the sidewall of the hole portion, and adapted to undergo a change in charge amount upon receiving light, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region formed in a top surface of the first-conductive type planar semiconductor layer and in a part of an upper region of the remaining part of the sidewall of the hole portion, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region.

摘要翻译： 旨在提供一种能够减小读通道的面积以增加受光部的表面积与一个像素的整个表面积的比率的固态图像拾取元件。 固体摄像元件包括形成在第二导电型平面半导体层上的第一导电型平面半导体层，形成在第一导电型平面半导体层中以在其中限定孔的孔部分，第一导电型 形成在孔部的底壁中的高浓度杂质区域，形成在孔部的侧壁的一部分中并与第一导电型高的部分连接的第一导电型高浓度杂质掺杂元素隔离区 - 浓度杂质区域，形成在第一导电型高浓度杂质区域下方的第二导电型光电转换区域和在孔部分的侧壁的剩余部分的下部区域的一部分中，并且适于经受 接收光时的电荷量的变化，通过栅极电介质膜形成在孔部的侧壁上的转印电极，第二导电型CC D沟道区，形成在所述第一导电型平面状半导体层的上表面和所述孔部的所述侧壁的剩余部分的上部区域的一部分中的第一导电区，以及形成在所述第一导电型 夹在第二导电型光电转换区域和第二导电型CCD沟道区域之间的平面型半导体层。

公开(公告)号：US07645658B2

公开(公告)日：2010-01-12

申请号：US11976216

申请日：2007-10-23

申请人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

发明人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

IPC分类号： H01L21/8238

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/66068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film. Furthermore, a dehydration process is performed at about 700° C. or lower in an inert gas atmosphere after the reflow process is performed.

摘要翻译： 制造具有MOS结构的碳化硅半导体器件的方法包括制备由碳化硅制成的衬底，并形成沟道区，第一杂质区，第二杂质区，栅绝缘层和栅电极，以形成 半导体元件。 此外，在半导体元件上形成膜以提供层间绝缘层的材料，并且在湿气氛中在约700℃或更高的温度下进行回流工艺，使得层间绝缘层由 这个电影。 此外，在进行回流处理之后，在惰性气体气氛中，在约700℃以下进行脱水处理。