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    TECHNIQUES TO FACILITATE A HARDWARE BASED TABLE LOOKUP
    81.
    发明申请
    TECHNIQUES TO FACILITATE A HARDWARE BASED TABLE LOOKUP 审中-公开

    公开(公告)号：US20190310937A1

    公开(公告)日：2019-10-10

    申请号：US16452173

    申请日：2019-06-25

    Applicant: Intel Corporation

    Inventor： Alexander BACHMUTSKY ,  Raghu KONDAPALLI ,  Francesc GUIM BERNAT

    IPC: G06F12/06

    Abstract: Techniques to facilitate a hardware based table look of a table maintained in or more types of memories or memory domains include examples of receiving a search request forwarded from a queue management device. Examples also include implementing table lookups to obtain a result and sending the result to an output queue of the queue management device for the queue management device to forward the result to a requestor of the search request.

    DATA MANAGEMENT FOR EDGE ARCHITECTURES
    82.
    发明申请
    DATA MANAGEMENT FOR EDGE ARCHITECTURES 审中-公开

    公开(公告)号：US20190278631A1

    公开(公告)日：2019-09-12

    申请号：US16422905

    申请日：2019-05-24

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Ramanathan SETHURAMAN ,  Karthik KUMAR ,  Mark A. SCHMISSEUR ,  Brinda GANESH

    IPC: G06F9/50 ,  G06F9/54

    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.

    TECHNIQUES FOR BATCH OPERATIONS TO STORAGE DEVICES
    85.
    发明申请
    TECHNIQUES FOR BATCH OPERATIONS TO STORAGE DEVICES 审中-公开

    公开(公告)号：US20190102107A1

    公开(公告)日：2019-04-04

    申请号：US15721441

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT

    IPC: G06F3/06

    Abstract: Examples include techniques to manage or process batch access operations to storage devices. Examples include receiving a batch access operation request to remotely access storage devices. The batch access operations request included in a fabric packet routed to a target host computing node coupled with the storage devices through a networking fabric. A granted batch access operation request having multiple read/write transactions to or from selected storage devices.

    ADAPTIVE ROUTING FOR POOLED AND TIERED DATA ARCHITECTURES
    89.
    发明申请
    ADAPTIVE ROUTING FOR POOLED AND TIERED DATA ARCHITECTURES 有权

    公开(公告)号：US20250086123A1

    公开(公告)日：2025-03-13

    申请号：US18894967

    申请日：2024-09-24

    Applicant: Intel Corporation

    Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT

    IPC: G06F12/14 ,  G06F12/06 ,  G06F12/0813 ,  G06F12/0891

    Abstract: In an embodiment, network device apparatus is provided that includes packet processing circuitry to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request, and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, may cause transmission of the memory access request to the different device. The memory access request may comprise an identifier of a requester of the memory access request and the identifier may comprise a Process Address Space identifier (PASID).

    IPU BASED OPERATORS
    90.
    发明公开
    IPU BASED OPERATORS 审中-公开

    公开(公告)号：US20240223384A1

    公开(公告)日：2024-07-04

    申请号：US18558155

    申请日：2021-09-17

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT

    IPC: H04L9/32

    CPC classification number: H04L9/3263 ,  H04L9/3236

    Abstract: Methods and apparatus for attestation and execution of operators. The apparatus is configured to be implemented in a compute platform including at least one processing unit, and is configured to perform client-side attestation operations with an operator attestation service to validate an operator to be executed on the apparatus or a processing unit on the compute platform. The apparatus is also configured to fetch an operator from an operator catalog, compute a hash over the operator, and send a message containing the hash and operator identifier (ID) (or digest containing the same with optional signing) to the operator attestation service, which validates the operator by looking up a valid hash for the operator using the operator ID and comparing the hashes. The apparatus is also configured to maintain and enforce tenant rules relating to execution of operators, and includes a cache for caching validated operators.

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