公开(公告)号：US20200066893A1

公开(公告)日：2020-02-27

申请号：US16321722

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pavel M. AGABABOV

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor transistor structure is described. In an example, the semiconductor transistor includes a group III-N semiconductor material disposed on a doped buffer layer, above a substrate. A polarization charge inducing layer is disposed on and conformal with the sloped sidewalls and a planar uppermost surface of the group III-N semiconductor material. A gate structure is disposed on the sloped sidewalls. A source contact is formed on an uppermost portion of the polarization charge inducing layer. A drain region is formed adjacent to the doped buffer layer. An insulator layer is disposed on the drain region and separates the gate structure from the drain region.

公开(公告)号：US20200066890A1

公开(公告)日：2020-02-27

申请号：US16321789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/45 ,  H01L29/66 ,  H01L29/861 ,  H01L27/06

Abstract: A transistor connected diode structure is described. In an example, the transistor connected diode structure includes a group III-N semiconductor material disposed on substrate. A raised source structure and a raised drain structure are disposed on the group III-N semiconductor material. A mobility enhancement layer is disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the mobility enhancement layer, the polarization charge inducing layer having a first portion and a second portion separated by a gap. A gate dielectric layer disposed on the mobility enhancement layer in the gap. A first metal electrode having a first portion disposed on the raised drain structure, a second portion disposed above the second portion of the polarization charge inducing layer and a third portion disposed on the gate dielectric layer in the gap. A second metal electrode disposed on the raised source structure.

公开(公告)号：US20200066849A1

公开(公告)日：2020-02-27

申请号：US16322453

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/20 ,  H01L29/868 ,  H01L29/66 ,  H01L29/205

Abstract: A P-i-N diode structure includes a group III-N semiconductor material disposed on a substrate. An n-doped raised drain structure is disposed on the group III-N semiconductor material. An intrinsic group III-N semiconductor material is disposed on the n-doped raised drain structure. A p-doped group III-N semiconductor material is disposed on the intrinsic group III-N semiconductor material. A first electrode is connected to the p-doped group III-N semiconductor material. A second electrode is electrically coupled to the n-doped raised drain structure. In an embodiment, a group III-N transistor is electrically coupled to the P-i-N diode. In an embodiment, a group III-N transistor is electrically isolated from the P-i-N diode. In an embodiment, a gate electrode and an n-doped raised drain structure are electrically coupled to the n-doped raised drain structure and the second electrode of the P-i-N diode to form the group III-N transistor.

公开(公告)号：US20200058782A1

公开(公告)日：2020-02-20

申请号：US16461353

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.

公开(公告)号：US20200006322A1

公开(公告)日：2020-01-02

申请号：US16024705

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Paul FISCHER ,  Walid HAFEZ ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L27/06 ,  H01L29/872 ,  H01L21/8252 ,  H01L27/02 ,  H01L29/205 ,  H01L29/20

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393211A1

公开(公告)日：2019-12-26

申请号：US16016419

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Paul FISCHER ,  Walid HAFEZ ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L27/02 ,  H01L29/10 ,  H01L27/06 ,  H01L21/265

Abstract: A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.

公开(公告)号：US20190341899A1

公开(公告)日：2019-11-07

申请号：US16349935

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Paul FISCHER ,  Mark RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H03H3/02 ,  H03H9/17 ,  H03H9/60

Abstract: Modern RF front end filters feature acoustic resonators in a film bulk acoustic resonator (FBAR) structure. An acoustic filter is a circuit that includes at least (and typically significantly more) two resonators. The acoustic resonator structure comprises a substrate including sidewalls and a vertical cavity between the sidewalls and two or more resonators deposited in the vertical cavity.

公开(公告)号：US20190304896A1

公开(公告)日：2019-10-03

申请号：US16462889

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines

公开(公告)号：US20190287935A1

公开(公告)日：2019-09-19

申请号：US16345627

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Paul B. FISCHER ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L23/66 ,  H01L23/14 ,  H01L23/13 ,  H01L23/522 ,  H01L21/50

Abstract: Embodiments of the invention include a microelectronic device that includes an insulating substrate, a RF transistor layer, and an interconnect structure disposed on the RF transistor layer. The RF transistor layer includes RF transistors for microwave frequencies. The interconnect structure includes at least one layer of dielectric material and a conductive layer having a plurality of conductive lines. The insulating substrate reduces parasitic capacitances and parasitic coupling to the insulating substrate.

公开(公告)号：US20190067081A1

公开(公告)日：2019-02-28

申请号：US16083859

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Seung Hoon SUNG

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L29/20 ,  H01L33/20 ,  H01L33/44

Abstract: A method of fabricating a wafer is disclosed. The method includes forming a protective layer on a device side and a non-device side of a substrate of the wafer. The method further includes removing the protective layer from a center portion of the device side of the substrate while retaining the protective layer in an edge portion of the substrate. The method also includes forming semiconductor layer in the center portion of the device side of the substrate while the protective layer is in the edge portion of the substrate.