公开(公告)号：US10831446B2

公开(公告)日：2020-11-10

申请号：US16145569

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Abhishek Sharma ,  Ian A. Young

IPC: G06F7/544 ,  G06F17/16 ,  G06F7/501 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063

Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit×n-bit multiplications.

公开(公告)号：US10579335B2

公开(公告)日：2020-03-03

申请号：US15627526

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Vikram B. Suresh ,  Raghavan Kumar

IPC: G06F7/52 ,  G06F7/523 ,  G06F21/72 ,  G06F21/60

Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a plurality of partial products associated with a multiply operation; partition the plurality of partial products into a first set of partial products, a second set of partial products, and a third set of partial products; determine whether the multiply operation is associated with a square operation; upon a determination that the multiply operation is associated with the square operation, compute a result based on the first set of partial products and the third set of partial products; and upon a determination that the multiply operation is not associated with the square operation, compute the result based on the first set of partial products, the second set of partial products, and the third set of partial products.

公开(公告)号：US20190325166A1

公开(公告)日：2019-10-24

申请号：US16456339

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Rafael Misoczki ,  Santosh Ghosh ,  Raghavan Kumar ,  Manoj Sastry ,  Andrew H. Reinders

IPC: G06F21/72 ,  G06F21/76 ,  H04L9/32 ,  H04L9/08

Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

公开(公告)号：US20190319782A1

公开(公告)日：2019-10-17

申请号：US16455950

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： SANTOSH GHOSH ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  H04L9/32 ,  G06F9/30 ,  G06F7/503

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US20190197391A1

公开(公告)日：2019-06-27

申请号：US15855813

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Gregory Kengho Chen ,  Phil Christopher Knag ,  Ram Kumar Krishnamurthy ,  Raghavan Kumar ,  Huseyin Ekin Sumbul

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: Systems and methods may apply homeostatic plasticity control in a spiking neural network, such as at a neuron of a core of the spiking neural network. The neuron may receive input spike information and determine whether to activate an output spike at the neuron based at least in part on the input spike information and a bias value. The bias value may be set based on whether the neuron issued a previous output spike during a previous time period. The bias value may be updated based on whether the output spike was activated at the neuron. For example, in accordance with a determination to activate the output spike, the bias value may be decreased, and in accordance with a determination to not activate the output spike, the bias value may be increased.

公开(公告)号：US20190043560A1

公开(公告)日：2019-02-07

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C11/418 ,  G06F7/544 ,  G06F9/30 ,  G11C13/00 ,  G11C11/419

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

公开(公告)号：US20190042910A1

公开(公告)日：2019-02-07

申请号：US15845245

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Ram Kumar Krishnamurthy ,  Gregory Kengho Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Huseyin Ekin Sumbul

IPC: G06N3/04

Abstract: System and techniques for spike timing dependent plasticity (STDP) in neuromorphic hardware are described herein. A first spike may be received, at a first neuron at a first time, from a second neuron. The first neuron may produce a second spike at a second time after the first time. At a third time after the second time, the first neuron may receive a third spike from the second neuron. Here, the third spike is a replay of the first spike with a defined time offset. The first neuron may then perform long term potentiation (LTP) for the first spike using the third spike.

公开(公告)号：US10103873B2

公开(公告)日：2018-10-16

申请号：US15088823

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Sudhir K. Satpathy ,  Vikram B. Suresh

IPC: G06F11/30 ,  H04L9/00 ,  H04L9/06 ,  G06F12/14

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.

公开(公告)号：US20180097618A1

公开(公告)日：2018-04-05

申请号：US15283000

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Avinash L. Varna ,  Vikram B. Suresh ,  Sudhir K. Satpathy

IPC: H04L9/06 ,  G11C19/00 ,  H03K19/21 ,  H04L9/00 ,  H04L9/08

CPC classification number: H04L9/0662 ,  G09C1/00 ,  G11C19/00 ,  H03K19/215 ,  H04L9/003 ,  H04L9/0631 ,  H04L2209/046 ,  H04L2209/125

Abstract: Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

公开(公告)号：US20170286829A1

公开(公告)日：2017-10-05

申请号：US15088198

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin E. Sumbul

IPC: G06N3/08 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: Systems and methods for event-driven learning with spike timing dependent plasticity in neuromorphic computers are disclosed. A neuromorphic processor includes a synapse coupled to a pre-synaptic neuron and coupled to a post-synaptic neuron, the synapse including a synapse memory to store a synapse weight and synapse spike timing dependent plasticity (STDP) circuit coupled to the synapse memory. The pre-synaptic neuron includes a pre-synaptic neuron memory to store a pre-synaptic neuron spike history and a pre-synaptic neuron STDP circuit coupled to the pre-synaptic neuron memory, the pre-synaptic neuron STDP circuit to, in response to the pre-synaptic neuron firing, initiate performing long term potentiation. The post-synaptic neuron includes a post-synaptic neuron memory storing a post-synaptic neuron spike history and a post-synaptic neuron STDP circuit coupled to the post-synaptic neuron memory to, in response to the post-synaptic neuron firing, initiate performing long term depression.