公开(公告)号：US11153968B2

公开(公告)日：2021-10-19

申请号：US15841880

申请日：2017-12-14

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Yun Ling ,  Chia Voon Tan

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: Techniques and mechanisms for mitigating the effect of signal noise on communication via an interconnect. In an embodiment, a substrate includes an interconnect and a conductor which has a hole formed therein. Portions of the interconnect variously extend over a side of the conductor, wherein another recess portion of the interconnect extends from a plane which includes the side, and further extends at least partially into the hole. The configuration of the recess portion extending within the hole may contribute to an impedance which dampens a transmitter slew rate of the communication. In an embodiment, a total distance along a path formed by the interconnect is equal to or less than 5.5 inches.

公开(公告)号：US20210183776A1

公开(公告)日：2021-06-17

申请号：US17025990

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

公开(公告)号：US10985147B2

公开(公告)日：2021-04-20

申请号：US16017719

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Chin Lee Kuan

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498

Abstract: A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.

公开(公告)号：US10943792B2

公开(公告)日：2021-03-09

申请号：US16325665

申请日：2016-09-27

Applicant: Intel Corporation ,  Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Howe Yin Loo

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L29/06 ,  H01L23/00 ,  H01L25/18

Abstract: A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.

公开(公告)号：US10916524B2

公开(公告)日：2021-02-09

申请号：US16473570

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Ping Ping Ooi

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L27/06 ,  H01L27/08

Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.

公开(公告)号：US10716209B2

公开(公告)日：2020-07-14

申请号：US16565639

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC: H05K1/11 ,  H05K3/40 ,  H05K1/03 ,  H05K3/46

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

公开(公告)号：US20200168592A1

公开(公告)日：2020-05-28

申请号：US16774904

申请日：2020-01-28

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Boon Ping Koh ,  Kooi Chi Ooi

IPC: H01L25/16 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/00 ,  H01Q1/52 ,  H01Q21/22 ,  H01L23/498 ,  H01L25/00 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66

Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.

公开(公告)号：US20200168528A1

公开(公告)日：2020-05-28

申请号：US16663001

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/768 ,  H01L25/00

Abstract: Disclosed embodiments include a multi-chip package that includes an embedded reference plane between two stacked semiconductive devices, with through-silicon vias that penetrate the reference plane, including reference-voltage vias that contact the reference plane, and signal and power-delivery vias that are insulated from the reference plane. A third semiconductive device is seated with active devices and metallization on the second conductive device.

公开(公告)号：US20200027813A1

公开(公告)日：2020-01-23

申请号：US16453605

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Ping Ping Ooi

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/552

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a base package, an ancillary package, and an electrically isolated metal layer. The base package may include a base die. The ancillary package may include an ancillary component. The ancillary package may be located on top of the base package. The electrically isolated metal layer may be located at least partially within a layer of the base package such that a portion of the electrically isolated metal layer contacts at least one surface of the base die and is located in between the base die and the ancillary component.

公开(公告)号：US10541200B2

公开(公告)日：2020-01-21

申请号：US15982912

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Ping Ping Ooi ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Mooi Ling Chang ,  Wen Wei Lum

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/367 ,  H01L23/50

Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage. One or more conductive traces may connect the conductive features in the interior with conductive features in the periphery.