公开(公告)号：US08321773B1

公开(公告)日：2012-11-27

申请号：US12262666

申请日：2008-10-31

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： G06F11/00

CPC分类号： G06F7/588 ,  G06F21/554 ,  G06F21/71 ,  G06F21/86

摘要： Circuits and methods to generate a True Random Number Generator (TRNG) with tamper-detection are presented. In one embodiment, the circuit includes two identical TRNG circuits and logic circuitry that combines and correlates the outputs of the two TRNG circuits. The two identical TRNG circuits are located in close proximity to each other inside an Integrated Circuit (IC). The logic circuitry analyzes the outputs of the two TRNG circuits and the historical values of the relation between the outputs of the two TRNG circuits to determine if the outputs are correlated. If the outputs are not correlated, the logic circuitry outputs a true random number sequence based on the combination of the two TRNG circuits. As a result, circuit tampering, such as changes in temperature or voltage supplies, is detected in the IC.

摘要翻译： 介绍了使用篡改检测来生成真随机数发生器（TRNG）的电路和方法。 在一个实施例中，电路包括两个相同的TRNG电路和逻辑电路，其组合和相关两个TRNG电路的输出。 两个相同的TRNG电路位于集成电路（IC）内彼此靠近的位置。 逻辑电路分析两个TRNG电路的输出和两个TRNG电路的输出之间的关系的历史值，以确定输出是否相关。 如果输出不相关，则逻辑电路基于两个TRNG电路的组合输出真正的随机数序列。 结果，在IC中检测到电路篡改，例如温度变化或电压供应。

公开(公告)号：US07872903B2

公开(公告)日：2011-01-18

申请号：US12407762

申请日：2009-03-19

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C7/20 ,  G11C11/4125 ,  H03K19/00392 ,  H03K19/177 ,  H03K19/1776 ,  H03K19/17764

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.

摘要翻译： 提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。 存储元件可以各自具有十个晶体管，其包括互连以形成双稳态元件的两个地址晶体管和四个晶体管对。 诸如真实和补充清除线之类的清除线可以被路由到与某些晶体管对相关联的正电源端子和接地电源端子。 在清除操作期间，可以使用清除线选择性地削弱部分或全部晶体管对。 这有助于明确的操作，其中逻辑零值通过地址晶体管驱动并且减小交叉电流浪涌。

公开(公告)号：US20090161738A1

公开(公告)日：2009-06-25

申请号：US12283652

申请日：2008-09-15

申请人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

发明人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC分类号： H04L7/00 ,  H04B1/38

CPC分类号： H04L25/14

摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

公开(公告)号：US6066960A

公开(公告)日：2000-05-23

申请号：US82878

申请日：1998-05-21

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17728

摘要： AND gates are used at the inputs to logic elements in a programmable logic device. This allows more efficient configuration of the logic elements for basic functions such as a multiplier, clearable counter and multiplexer. Inputs to the AND gates are enabled by LAB-wide control signals that are distributed to several logic elements within a logic array block. The control signals can also be generated from a RAM or ROM, or by decoding existing control signals.

摘要翻译： 在可编程逻辑器件中的逻辑元件的输入端使用与门。 这允许更有效地配置用于基本功能的逻辑元件，例如乘法器，可清除计数器和多路复用器。 与门的输入由分布在逻辑阵列块内的多个逻辑元件的LAB范围的控制信号使能。 控制信号也可以从RAM或ROM生成，或通过解码现有的控制信号。

公开(公告)号：US06043676A

公开(公告)日：2000-03-28

申请号：US825821

申请日：1997-03-28

申请人： David W. Mendel ,  Brent A. Fairbanks ,  Bruce B. Pedersen

发明人： David W. Mendel ,  Brent A. Fairbanks ,  Bruce B. Pedersen

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： A programmable logic device (10) has a number of programmable logic elements (LES) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). An LAB incorporates one or more wide-input AND gates (74) for selectively combining the outputs of any number of LEs and producing a signal that is a logical combination of any number of its LEs. In variations of the invention, input signals may be selectively coupled to an AND gate by means of an OR gate (78) and may be selectively inverted by means of an XOR gate (76). A digital information processing system (500) incorporating the invention is disclosed. Various circuit techniques are provided for efficient implementation of a fast and wide exclusive OR or exclusive NOR function. A logic array block is equipped with a dedicated exclusive OR circuit with programmable inputs connected to selected terms from various logic cells, or outputs of the various logic cells. Another embodiment allows creating an embedded chain of exclusive OR gates to implement a wide exclusive OR gate by cascading a smaller exclusive OR gate within several logic cells.

摘要翻译： 可编程逻辑器件（10）具有多个可编程逻辑元件（LES）（12），它们被分组在多个逻辑阵列块（LAB）中。 LAB包括一个或多个宽输入与门（74），用于选择性地组合任何数量的LE的输出，并产生作为任何数量的LE的逻辑组合的信号。 在本发明的变型中，输入信号可以通过或门（78）选择性地耦合到与门，并且可以通过异或门（76）选择性地反相。 公开了结合本发明的数字信息处理系统（500）。 提供了各种电路技术，用于有效地实现快速和宽泛的异或或异或NOR功能。 逻辑阵列块配备有专用异或电路，其可编程输入连接到来自各种逻辑单元的选定项或各种逻辑单元的输出。 另一实施例允许创建异或门的嵌入链以通过级联多个逻辑单元内的较小的异或门来实现宽的异或门。

公开(公告)号：US5936425A

公开(公告)日：1999-08-10

申请号：US96250

申请日：1998-06-11

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/1737 ,  H03K19/1778

摘要： Each output signal of programmable logic circuitry is made programmably available to drive one or more of a plurality of tri-statable input/output pins of the circuitry. Each output signal is also made programmably available to provide the output enable signal for one or more of a multiplicity of those input/output pins. The above-mentioned plurality and multiplicity associated with each output signal may include the same or different input/output pins. Output signals may therefore be routed to the input/output pins with greater flexibility, and output enable signal options are also greatly increased.

摘要翻译： 可编程逻辑电路的每个输出信号被编程地可用于驱动电路的多个三态输入/输出引脚中的一个或多个。 每个输出信号也可编程地可用于为多个输入/输出引脚中的一个或多个提供输出使能信号。 与每个输出信号相关联的上述多个和多重可以包括相同或不同的输入/输出引脚。 因此，输出信号可以以更大的灵活性被路由到输入/输出引脚，并且输出使能信号选项也大大增加。

公开(公告)号：US5898318A

公开(公告)日：1999-04-27

申请号：US497100

申请日：1995-06-30

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LEs are connectable to one another via cascade connectors (72) between LEs. The cascade is enhanced by providing a selector (90) that allows a cascade line from one LE to selectively be coupled to an input of an adjacent or nearby LE through a cascade logic gate (94).

摘要翻译： 可编程逻辑器件（10）具有多个可编程逻辑元件（LE）（12），它们被分组在多个逻辑阵列块（LAB）中。 提供了一种全局互连结构（20,24），用于将LAB与其他LAB相互连接。 相邻或附近的LE可通过LE之间的级联连接器（72）彼此连接。 通过提供允许来自一个LE的级联线通过级联逻辑门（94）选择性地耦合到相邻或附近LE的输入的选择器（90）来增强级联。

公开(公告)号：US5859542A

公开(公告)日：1999-01-12

申请号：US898541

申请日：1997-07-22

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABS) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LEs are connectable to one another via cascade connectors (72) between LEs. The cascade is enhanced by providing a selector (90) that allows a cascade line from one LE to selectively be coupled to an input of an adjacent or nearby LE through a cascade logic gate (94).

摘要翻译： 可编程逻辑器件（10）具有多个可编程逻辑元件（LE）（12），它们被组合在多个逻辑阵列块（LABS）（14）中。 提供了一种全局互连结构（20,24），用于将LAB与其他LAB相互连接。 相邻或附近的LE可通过LE之间的级联连接器（72）彼此连接。 通过提供允许来自一个LE的级联线通过级联逻辑门（94）选择性地耦合到相邻或附近LE的输入的选择器（90）来增强级联。

公开(公告)号：US5815003A

公开(公告)日：1998-09-29

申请号：US497632

申请日：1995-06-30

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). An LE incorporates a plurality of partitioned look-up tables (40a, 40b) that may be selectively connected to its inputs and outputs by means of a number of multiplexers (44a-d, 46). Shared LAB-wide input lines (43a, 43b) provide a shared input line into a number of LEs in a LAB. A digital information processing system (500) incorporating the invention is disclosed. A wide-input AND gate (74) combining the outputs of a number of LEs is disclosed.

摘要翻译： 可编程逻辑器件（10）具有多个可编程逻辑元件（LE）（12），它们被分组在多个逻辑阵列块（LAB）中。 LE包括多个分割的查找表（40a，40b），其可以通过多个多路复用器（44a-d，46）选择性地连接到其输入和输出。 共享LAB宽输入线（43a，43b）为LAB中的许多LE提供共享输入线。 公开了结合本发明的数字信息处理系统（500）。 公开了组合多个LE的输出的宽输入与门（74）。

公开(公告)号：US5787009A

公开(公告)日：1998-07-28

申请号：US603222

申请日：1996-02-20

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Partitioning of a circuit design to facilitate economical implementation of that circuit in a physical circuit that is made up of two or more physical subcircuits is improved by starting with two different, conventionally produced partitions of the design and combining selected features of those two starting partitions to produce a final partition that is better than either of the starting partitions.