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106 条记录 (耗时 0.026 秒)

    Capacitor formed on a recrystallized polysilicon layer
    81.
    发明授权
    Capacitor formed on a recrystallized polysilicon layer 有权
    在再结晶的多晶硅层上形成的电容器

    公开(公告)号：US08053296B2

    公开(公告)日：2011-11-08

    申请号：US12478512

    申请日：2009-06-04

    申请人： Jiong-Ping Lu ,  Haowen Bu ,  Clint Montgomery

    发明人： Jiong-Ping Lu ,  Haowen Bu ,  Clint Montgomery

    IPC分类号： H01L21/00

    CPC分类号： H01L28/40 ,  H01L27/1085

    摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.

    摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 除了其他元件之外，半导体器件包括位于栅电极层143上的再结晶多晶硅层148，位于再结晶多晶硅层148上的电容器170.在该实施例中，电容器170包括第一电极173，绝缘体175 位于第一电极173上方，以及位于绝缘体175上方的第二电极178。

    FUSI integration method using SOG as a sacrificial planarization layer
    83.
    发明授权
    FUSI integration method using SOG as a sacrificial planarization layer 有权
    使用SOG作为牺牲平坦化层的FUSI积分方法

    公开(公告)号：US07943499B2

    公开(公告)日：2011-05-17

    申请号：US12603169

    申请日：2009-10-21

    申请人： Jiong-Ping Lu ,  Yaw S. Obeng ,  Ping Jiang ,  Joe G. Tran

    发明人： Jiong-Ping Lu ,  Yaw S. Obeng ,  Ping Jiang ,  Joe G. Tran

    IPC分类号： H01L21/28 ,  H01L21/44

    CPC分类号： H01L21/31055 ,  H01L21/28097 ,  H01L21/32134 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

    摘要翻译： 一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露 在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。 如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。

    CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER
    85.
    发明申请
    CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER 有权
    电容器在重组多晶硅层上形成

    公开(公告)号：US20100159665A1

    公开(公告)日：2010-06-24

    申请号：US12478512

    申请日：2009-06-04

    申请人： Jiong-Ping Lu ,  Haowen Bu ,  Clint Montgomery

    发明人： Jiong-Ping Lu ,  Haowen Bu ,  Clint Montgomery

    IPC分类号： H01L21/02

    CPC分类号： H01L28/40 ,  H01L27/1085

    摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.

    摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 除了其他元件之外，半导体器件包括位于栅电极层143上的再结晶多晶硅层148，位于再结晶多晶硅层148上的电容器170.在该实施例中，电容器170包括第一电极173，绝缘体175 位于第一电极173上方，以及位于绝缘体175上方的第二电极178。

    FUSI Integration Method Using SOG as a Sacrificial Planarization Layer
    87.
    发明申请
    FUSI Integration Method Using SOG as a Sacrificial Planarization Layer 有权
    使用SOG作为牺牲平面化层的FUSI集成方法

    公开(公告)号：US20100041231A1

    公开(公告)日：2010-02-18

    申请号：US12603169

    申请日：2009-10-21

    申请人： Jiong-Ping Lu ,  Yaw S. Obeng ,  Ping Jiang ,  Joe G. Tran

    发明人： Jiong-Ping Lu ,  Yaw S. Obeng ,  Ping Jiang ,  Joe G. Tran

    IPC分类号： H01L21/30

    CPC分类号： H01L21/31055 ,  H01L21/28097 ,  H01L21/32134 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

    摘要翻译： 一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露 在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。 如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除。

    Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device
    88.
    发明授权
    Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device 有权
    用独立的栅极和源极/漏极掺杂形成完全硅化半导体器件的方法及相关器件

    公开(公告)号：US07585738B2

    公开(公告)日：2009-09-08

    申请号：US11741540

    申请日：2007-04-27

    申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    IPC分类号： H01L21/336 ,  H01L21/44

    CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

    摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

    摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

    Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes
    90.
    发明申请
    Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes 审中-公开
    用于检测栅极电介质穿透的Ebeam检查和/或用于具有金属栅电极的晶体管的不完全硅化或金属化事件

    公开(公告)号：US20080176345A1

    公开(公告)日：2008-07-24

    申请号：US11655483

    申请日：2007-01-19

    申请人： Shaofeng Yu ,  Richard L. Guldi ,  Jiong-Ping Lu ,  Freidoon Mehrad ,  Jae Hyun Park

    发明人： Shaofeng Yu ,  Richard L. Guldi ,  Jiong-Ping Lu ,  Freidoon Mehrad ,  Jae Hyun Park

    IPC分类号： H01L21/66

    CPC分类号： H01L22/14

    摘要： Gate dielectric punch through and/or incomplete silicidation or metallization events that may occur during transistor formation are identified. The events are identified just after gate electrodes are formed in order to characterize the degree of faulty transistors for process control purposes and to scrap product if sufficiently defective so that subsequent resources are not unnecessarily expended. An electron beam or ebeam is directed at locations of a workpiece whereon on or more transistors are formed. Electrons that are resultantly emitted from these locations are detected and used to develop respective gray level values (GLV's). Gate dielectric punch through and/or incomplete silicidation or metallization events are identified by finding high or low GLV's relative to neighboring areas.

    摘要翻译： 识别在晶体管形成期间可能发生的栅极电介质穿透和/或不完全的硅化或金属化事件。 在形成栅极电极之后才识别事件，以便表征用于过程控制目的的故障晶体管的程度，并且如果充分有缺陷，则废弃产品，使得后续资源不会被不必要地消耗。 电子束或ebeam被引导到其上形成有多个晶体管的工件的位置。 从这些位置发射的电子被检测并用于开发各自的灰度值（GLV's）。 通过相对于相邻区域发现高或低GLV来鉴定栅极电介质穿透和/或不完全硅化或金属化事件。