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124 条记录 (耗时 0.036 秒)

    Device including a resistive path to introduce an equivalent RC circuit
    81.
    发明授权
    Device including a resistive path to introduce an equivalent RC circuit 有权

    公开(公告)号：US06800924B2

    公开(公告)日：2004-10-05

    申请号：US10393537

    申请日：2003-03-20

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L2900

    CPC分类号： H01L27/092 ,  H01L27/0727 ,  H01L29/1087 ,  H01L29/8605

    摘要： Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

    Device including a resistive path to introduce an equivalent RC circuit
    82.
    发明授权
    Device including a resistive path to introduce an equivalent RC circuit 有权
    装置包括引入等效RC电路的电阻路径

    公开(公告)号：US06777779B2

    公开(公告)日：2004-08-17

    申请号：US10393535

    申请日：2003-03-20

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L2900

    CPC分类号： H01L27/092 ,  H01L27/0727 ,  H01L29/1087 ,  H01L29/8605

    摘要： Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

    摘要翻译： 用于提供设备的结构，其包括专门设计成在装置的散装材料和井套接触之间提供预定电阻的电阻路径。 通过提供电阻路径，将等效的RC电路引入器件，其允许体材料电势跟踪栅极电位，从而有利地降低器件导通时的阈值电压，并在器件关断时提高阈值电压。 此外，引入电阻路径还允许大量材料电位被控制并且在切换事件之间处于平衡电位下稳定。

    Back-biased MOS device
    83.
    发明授权
    Back-biased MOS device 有权
    背偏MOS器件

    公开(公告)号：US06664608B1

    公开(公告)日：2003-12-16

    申请号：US09996705

    申请日：2001-11-30

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L2900

    CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L21/823878 ,  H01L27/092

    摘要： A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of p-wells.

    摘要翻译： 在本体材料的前侧形成有多个p阱和n阱，并且在散装材料的背面和多个n层之间交替地形成多个n层和p层， 井和井。 多个n层彼此电隔离并且将不同的电位分别路由到多个n阱中的选定的n阱，并且同样地，多个p层彼此电隔离并且分别将不同的电位路由到 多个对孔。

    Device including a resistive path to introduce an equivalent RC circuit
    84.
    发明授权
    Device including a resistive path to introduce an equivalent RC circuit 有权

    公开(公告)号：US06586817B1

    公开(公告)日：2003-07-01

    申请号：US09860253

    申请日：2001-05-18

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L2900

    CPC分类号： H01L27/092 ,  H01L27/0727 ,  H01L29/1087 ,  H01L29/8605

    摘要： Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

    Method for coupling logic blocks using low threshold pass transistors
    85.
    发明授权
    Method for coupling logic blocks using low threshold pass transistors 有权
    使用低阈值传递晶体管耦合逻辑块的方法

    公开(公告)号：US06489804B1

    公开(公告)日：2002-12-03

    申请号：US09872786

    申请日：2001-06-01

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H03K19173

    CPC分类号： H03K19/17784 ,  H03K17/063 ,  H03K19/17728 ,  H03K19/17792

    摘要： Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.

    摘要翻译： 可编程逻辑结构包括在非常低的电源电压下工作的逻辑块。 根据本发明，传输晶体管位于逻辑块之间。 由于本发明的逻辑块在非常低的电源电压下工作，所以传输晶体管可能被过载驱动，从而降低了增加的电阻。 在本发明的一个实施例中，传输晶体管是低阈值晶体管。 在该实施例中，传输晶体管也被过驱动以减少泄漏电流并进一步隔离逻辑块。

    Method for engineering the threshold voltage of a device using buried wells
    86.
    发明授权
    Method for engineering the threshold voltage of a device using buried wells 有权
    使用埋井设备的阈值电压的方法

    公开(公告)号：US06489224B1

    公开(公告)日：2002-12-03

    申请号：US09872419

    申请日：2001-05-31

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L21425

    CPC分类号： H01L21/823892

    摘要： Buried platform wells are specifically used to electrically interact with the platform transistors of the invention. The dopant concentration distribution of the buried platform wells is used to change the threshold voltage of the platform transistors of the invention by introducing a tail dopant concentration into the active region of the platform transistors. The platform transistors of the invention can also be used in conjunction with standard transistors, on a single structure, to provide both low and relatively high threshold voltage transistors on a single structure. Consequently, using the method and structure of the invention, considerable versatility and design flexibility are achieved with minimum additional structural complexity.

    摘要翻译： 埋地平台井专门用于与本发明的平台晶体管电相互作用。 掩埋平台阱的掺杂剂浓度分布用于通过将尾掺杂剂浓度引入平台晶体管的有源区来改变本发明的平台晶体管的阈值电压。 本发明的平台晶体管也可以与单个结构上的标准晶体管结合使用，以在单个结构上提供低和相对高的阈值电压晶体管。 因此，使用本发明的方法和结构，以最小的附加结构复杂性实现了相当多的通用性和设计灵活性。

    Low voltage latch with uniform stack height
    87.
    发明授权
    Low voltage latch with uniform stack height 有权
    具有均匀堆叠高度的低压闩锁

    公开(公告)号：US06472919B1

    公开(公告)日：2002-10-29

    申请号：US09872787

    申请日：2001-06-01

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H03K3356

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the invention is further increased by designing latches with uniform stack height components. One embodiment of the invention allows for minimum supply voltages of 60 millivolts, an improvement of over thirteen hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

    摘要翻译： 低压锁存器被设计成使得包括在锁存器中的所有晶体管都是低阈值晶体管，并且通过设计具有均匀堆栈高度分量的锁存器来进一步增加本发明的锁存器的电压可伸缩性。 与典型的现有技术的800毫伏的最小电压要求相比，本发明的一个实施例允许60毫伏的最小电源电压，改进超过百分之十三点。

    Method for reducing PN junction leakage
    88.
    发明授权
    Method for reducing PN junction leakage 有权
    减少PN结泄漏的方法

    公开(公告)号：US06348372B1

    公开(公告)日：2002-02-19

    申请号：US09648867

    申请日：2000-08-25

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L218238

    CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L27/1203

    摘要： To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

    摘要翻译： 为了减少在轻掺杂的体材料中形成的轻掺杂阱之间的边界处的p-n结泄漏，在该结处注入高浓度区域。 高浓度区域含有相当高的掺杂剂水平，因此降低了在结处的耗尽区域的宽度。 耗尽区域的减小的宽度又减少了结漏电。

    Low threshold voltage, high performance junction transistor
    89.
    发明授权
    Low threshold voltage, high performance junction transistor 失效
    低阈值电压，高性能结晶体管

    公开(公告)号：US5719422A

    公开(公告)日：1998-02-17

    申请号：US831659

    申请日：1997-04-09

    申请人： James B. Burr ,  Michael P. Brassington

    发明人： James B. Burr ,  Michael P. Brassington

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7832 ,  H01L29/7833

    摘要： Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.

    摘要翻译： 本文公开了具有埋电极的低阈值电压MOS器件。 这样的器件具有源极和漏极区域，其包括尖端区域和插塞区域。 掩埋电极具有位于插塞区域的底部之上的底部边界。 掩埋电极具有与器件的体积相同的导电类型（尽管在较高的掺杂剂浓度），当然，与器件的源极和漏极相反的导电类型。 应提供掩埋电极的确切掺杂剂浓度和位置，使MOS器件避免穿通。