中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

145 records (took 0.025 seconds)

    DISCOVERY OF HARDWARE CHARACTERISTICS OF DEEP LEARNING ACCELERATORS FOR OPTIMIZATION VIA COMPILER
    81.
    发明申请
    DISCOVERY OF HARDWARE CHARACTERISTICS OF DEEP LEARNING ACCELERATORS FOR OPTIMIZATION VIA COMPILER 有权

    公开(公告)号：US20250036950A1

    公开(公告)日：2025-01-30

    申请号：US18912182

    申请日：2024-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Aliasger Tayeb Zaidy ,  Marko Vitez ,  Eugenio Culurciello ,  Jaime Cummins ,  Andre Xian Ming Chang

    IPC: G06N3/08 ,  G06F8/41 ,  G06N3/04

    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A computing device running a compiler can interact and/or probe an integrated circuit device to identify hardware characteristics of the integrated circuit device in performing matrix computations. The compiler can generate and optimize a result of compilation from a description of an artificial neural network based at least in part on the hardware characteristics of the integrated circuit device. The result of compilation can include first data representative of parameters of the artificial neural network and second data representative of instructions executable by the integrated circuit device to generate an output of the artificial neural network based on the first data and an input to the artificial neural network.

    APPARATUSES AND METHODS FOR WRITE DATA PRECONDITIONING USING A NEURAL NETWORK
    82.
    发明申请
    APPARATUSES AND METHODS FOR WRITE DATA PRECONDITIONING USING A NEURAL NETWORK 有权

    公开(公告)号：US20240412796A1

    公开(公告)日：2024-12-12

    申请号：US18734766

    申请日：2024-06-05

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: G11C29/12 ,  G11C11/54 ,  G11C29/36

    Abstract: A memory includes a receiver circuit configured to receive write data via a data terminal, and a neural network based preconditioning circuit configured to receive a write data signal according to the write data. A neural network of the preconditioning circuit is configured to precondition the write data signal based on a characteristic of a write data path to provide a modified write data signal. The memory further includes a memory array configured to store the write data based on the modified write data signal.

    DETERMINING CHANNEL CHARACTERISTICS SYSTEMS AND METHODS
    84.
    发明申请
    DETERMINING CHANNEL CHARACTERISTICS SYSTEMS AND METHODS 有权

    公开(公告)号：US20240385977A1

    公开(公告)日：2024-11-21

    申请号：US18666457

    申请日：2024-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: G06F13/16 ,  H04L5/00

    Abstract: Apparatuses and methods for determining a channel characteristic are disclosed. The channel characteristic can be a characteristic of a channel between a memory controller and a memory. The channel characteristic is determined at the memory controller relating to logic levels of data written to or read from the memory over the channel, and transceiver settings of a transceiver of the memory controller are modified according to the determined characteristic. The channel characteristic can be determined based on storing a pilot signal at the memory controller, causing the pilot signal to be written to the memory, and comparing a read pilot signal corresponding to the written pilot signal with the stored pilot signal.

    COOPERATIVE LEARNING NEURAL NETWORKS AND SYSTEMS
    85.
    发明公开
    COOPERATIVE LEARNING NEURAL NETWORKS AND SYSTEMS 审中-公开

    公开(公告)号：US20240256869A1

    公开(公告)日：2024-08-01

    申请号：US18609221

    申请日：2024-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: G06N3/08 ,  G06N3/04 ,  G06N3/045 ,  H04W4/02 ,  H04W4/38 ,  H04W4/40 ,  H04W4/90

    CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/045 ,  H04W4/02 ,  H04W4/023 ,  H04W4/38 ,  H04W4/40 ,  H04W4/90

    Abstract: Systems, methods, and apparatuses related to cooperative learning neural networks are described. Cooperative learning neural networks may include neural networks which utilize sensor data received wirelessly from at least one other wireless communication device to train the neural network. For example, cooperative learning neural networks described herein may be used to develop weights which are associated with objects or conditions at one device and which may be transmitted to a second device, where they may be used to train the second device to react to such objects or conditions. The disclosed features may be used in various contexts, including machine-type communication, machine-to-machine communication, device-to-device communication, and the like. The disclosed techniques may be employed in a wireless (e.g., cellular) communication system, which may operate according to various standardized protocols.

    Apparatus and method to switch configurable logic units
    90.
    发明授权
    Apparatus and method to switch configurable logic units 有权

    公开(公告)号：US11507531B2

    公开(公告)日：2022-11-22

    申请号：US17184945

    申请日：2021-02-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: G06F15/78 ,  G06F9/38

    Abstract: Examples described herein include systems and methods which include an apparatus comprising a plurality of configurable logic units and a plurality of switches, with each switch being coupled to at least one configurable logic unit of the plurality of configurable logic units. The apparatus further includes an instruction register configured to provide respective switch instructions of a plurality of switch instructions to each switch based on a computation to be implemented among the plurality of configurable logic units. For example, the switch instructions may include allocating the plurality of configurable logic units to perform the computation and activating an input of the switch and an output of the switch to couple at least a first configurable logic unit and a second configurable logic unit. In various embodiments, configurable logic units can include arithmetic logic units (ALUs), bit manipulation units (BMUs), and multiplier-accumulator units (MACs).

Patent Agency Ranking