公开(公告)号：US06438677B1

公开(公告)日：2002-08-20

申请号：US09422028

申请日：1999-10-20

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F952

CPC分类号： G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that supports space and time dimensional program execution by facilitating accesses to different versions of a memory element. The system supports a head thread that executes program instructions and a speculative thread that executes program instructions in advance of the head thread. The head thread accesses a primary version of the memory element, and the speculative thread accesses a space-time dimensioned version of the memory element. During a reference to the memory element by the head thread, the system accesses the primary version of the memory element. During a reference to the memory element by the speculative thread, the speculative thread accesses a pointer associated with the primary version of the memory element, and accesses a version of the memory element through the pointer. Note that the pointer points to the space-time dimensioned version of the memory element if the space-time dimensioned version of the memory element exists. In one embodiment of the present invention, the pointer points to the primary version of the memory element if the space-time dimensioned version of the memory element does not exist.

摘要翻译： 本发明的一个实施例提供一种通过促进对存储器元件的不同版本的访问来支持空间和时间维度程序执行的系统。 该系统支持执行程序指令的头部线程和在头部线程之前执行程序指令的推测线程。 头线程访问存储器元件的主要版本，并且推测线程访问存储器元件的时空维度版本。 在通过头部线程引用存储器元件期间，系统访问存储器元件的主要版本。 在通过推测线程对存储器元件的引用期间，推测线程访问与存储器元件的主版本相关联的指针，并且通过指针访问存储器元件的版本。 请注意，如果内存元素的时空维度版本存在，则指针指向内存元素的时空维度版本。 在本发明的一个实施例中，如果存储元件的时空尺寸版本不存在，则指针指向存储元件的主版本。

公开(公告)号：US06353881B1

公开(公告)日：2002-03-05

申请号：US09313229

申请日：1999-05-17

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F952

CPC分类号： G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863

摘要： A system is provided that facilitates space and time dimensional execution of computer programs through selective versioning of memory elements located in a system heap. The system includes a head thread that executes program instructions and a speculative thread that simultaneously executes program instructions in advance of the head thread with respect to the time dimension of sequential execution of the program. The collapsing of the time dimensions is facilitated by expanding the heap into two space-time dimensions, a primary dimension (dimension zero), in which the head thread operates, and a space-time dimension (dimension one), in which the speculative thread operates. In general, each dimension contains its own version of an object and objects created by the thread operating in the dimension. The head thread generally accesses a primary version of a memory element and the speculative thread generally accesses a corresponding space-time dimensioned version of the memory element. During a write by the head thread, the system performs the write to all dimensions of the memory element. Note that if the dimensions are collapsed at this address a single update will update all time dimensions. It also checks status information associated with the memory element to determine if the memory element has been read by the speculative thread. If so, the system causes the speculative thread to roll back so that the speculative thread can read a result of the write operation.

摘要翻译： 提供了一种系统，其通过对位于系统堆中的存储器元件进行选择性版本化来促进计算机程序的空间和时间尺寸的执行。 该系统包括执行程序指令的头螺纹和相对于程序的顺序执行的时间维度在头部线程之前同时执行程序指令的推测线程。 通过将堆扩展到两个时空维度（头线程操作的主维度（维度零））和空时维度（维度一）来促进时间维度的崩溃，其中推测线程 操作。 通常，每个维度都包含自己的一个对象的版本，以及由维度中的线程创建的对象。 头部线程通常访问存储器元件的主要版本，并且推测线程通常访问存储器元件的对应的时空维度版本。 在头部线程的写入期间，系统对存储器元件的所有维进行写入。 请注意，如果维度在此地址中折叠，则单个更新将更新所有时间维。 它还检查与存储器元件相关联的状态信息以确定存储器元件是否已被推测性线程读取。 如果是这样，系统会使推测线程回滚，以便推测线程可以读取写入操作的结果。

公开(公告)号：US09256438B2

公开(公告)日：2016-02-09

申请号：US12354206

申请日：2009-01-15

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3857 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3867

摘要： A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.

摘要翻译： 计算机处理器管道具有架构寄存器文件和工作寄存器文件。 在工作寄存器文件中的位置被分配给指令之后，在工作寄存器文件中的条目的寿命由通过流水线中的指定级的预定数量的指令确定。 基于性能特征选择工作寄存器文件的大小。 工作寄存器文件债权人指示器耦合到前端管道部分和后端管道部分。 监视工作寄存器文件信用指示符，以防止工作寄存器文件溢出。 当架构寄存器文件中的一个位置被提前读取时，监视该位置以确定在发出与早期读取相关联的指令之前是否写入位置。

公开(公告)号：US20100180103A1

公开(公告)日：2010-07-15

申请号：US12354206

申请日：2009-01-15

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/38 ,  G06F9/312

CPC分类号： G06F9/3857 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3867

摘要： A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.

摘要翻译： 计算机处理器管道具有架构寄存器文件和工作寄存器文件。 在工作寄存器文件中的位置被分配给指令之后，在工作寄存器文件中的条目的寿命由通过流水线中的指定级的预定数量的指令确定。 基于性能特征选择工作寄存器文件的大小。 工作寄存器文件债权人指示器耦合到前端管道部分和后端管道部分。 监视工作寄存器文件信用指示符，以防止工作寄存器文件溢出。 当架构寄存器文件中的一个位置被提前读取时，监视该位置以确定在发出与早期读取相关联的指令之前是否写入位置。

公开(公告)号：US07664942B1

公开(公告)日：2010-02-16

申请号：US12197629

申请日：2008-08-25

申请人： Marc Tremblay ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F9/38

CPC分类号： G06F9/3889 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： Embodiments of the present invention provide a system that executes program code in a processor. The system starts by executing the program code in a normal mode using a primary strand while concurrently executing the program code ahead of the primary strand using a subordinate strand in a scout mode. Upon resolving a branch using the subordinate strand, the system records a resolution for the branch in a speculative branch resolution table. Upon subsequently encountering the branch using the primary strand, the system uses the recorded resolution from the speculative branch resolution table to predict a resolution for the branch for the primary strand. Upon determining that the resolution of the branch was mispredicted for the primary strand, the system determines that the subordinate strand mispredicted the branch. The system then recovers the subordinate strand to the branch and restarts the subordinate strand executing the program code.

摘要翻译： 本发明的实施例提供一种在处理器中执行程序代码的系统。 系统通过使用主链在正常模式下执行程序代码，同时使用侦察模式中的从属线同时执行主链前面的程序代码来开始。 在使用下级线解析分支时，系统在推测分支分辨率表中记录分支的分辨率。 在随后使用主链遇到分支时，系统使用来自推测性分支分辨率表的记录分辨率来预测主股的分支的分辨率。 在确定分支的决议对于主要股份进行了错误估计时，系统确定下级股错误地预测了分行。 系统然后将下级线路恢复到分支，并重新启动执行程序代码的下级线程。

公开(公告)号：US07584346B1

公开(公告)日：2009-09-01

申请号：US11698479

申请日：2007-01-25

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/48 ,  G06F12/14

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3842 ,  G06F12/0862

摘要： One embodiment of the present invention provides a system that supports different modes of multi-threaded speculative execution on a processor. The system starts with two or more threads executing in a first multi-threaded speculative-execution mode. The system then switches to a second multi-threaded speculative-execution mode by configuring circuits in the processor to enable a second multi-threaded speculative-execution mode. After configuring the circuits, the system next switches the threads from executing in the first multi-threaded speculative-execution mode to executing in the second multi-threaded speculative-execution mode.

摘要翻译： 本发明的一个实施例提供一种在处理器上支持不同模式的多线程推测性执行的系统。 系统以在第一个多线程推测执行模式下执行的两个或多个线程开始。 然后，系统通过配置处理器中的电路来启用第二多线程推测执行模式，然后切换到第二多线程推测执行模式。 在配置电路之后，系统接下来将线程从第一多线程推测执行模式执行到第二多线程推测执行模式。

公开(公告)号：US07277989B2

公开(公告)日：2007-10-02

申请号：US11083264

申请日：2005-03-16

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F12/00

CPC分类号： G06F9/3842 ,  G06F9/383 ,  G06F9/3834 ,  G06F12/0862

摘要： One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.

摘要翻译： 本发明的一个实施例提供一种处理器，其在推测执行期间选择性地取出用于存储指令的高速缓存行。 在正常执行期间，处理器以程序顺序发出执行指令。 当遇到产生发射条件的指令时，处理器执行检查点并以推测执行模式开始执行指令。 在推测执行模式期间遇到存储指令时，处理器检查L1数据高速缓存以获得匹配的高速缓存线，并将商店的存储缓冲区检查到匹配的高速缓存行。 如果在L1数据高速缓存中已经存在匹配的高速缓存行，或者如果存储到存储缓冲器中的存储到匹配的高速缓存行，则处理器抑制对高速缓存行的提取的生成。 否则，处理器生成缓存行的提取。

公开(公告)号：US07216219B2

公开(公告)日：2007-05-08

申请号：US10923218

申请日：2004-08-20

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/30

CPC分类号： G06F9/3863 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： One embodiment of the present invention provides a system that avoids write-after-read (WAR) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and wherein other non-deferred instructions are executed in program order. While deferring the instruction, the system stores the instruction along with any resolved source operands for the instruction into a deferred buffer.

摘要翻译： 本发明的一个实施例提供了一种在推测性地在处理器上执行指令时避免读后读取（WAR）危险的系统。 系统以正常执行模式启动，其中系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生检查点，延迟指令并执行执行模式中的后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他 非递延指令按程序顺序执行。 在延迟指令的同时，系统将指令与指令的任何解析的源操作数一起存储到延迟缓冲区中。

公开(公告)号：US20060271769A1

公开(公告)日：2006-11-30

申请号：US11495450

申请日：2006-07-28

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3863 ,  G06F9/3865

摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.

摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中其他非延迟指令以程序顺序执行。

公开(公告)号：US07127643B2

公开(公告)日：2006-10-24

申请号：US10288941

申请日：2002-11-06

申请人： Marc Tremblay ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F11/00

CPC分类号： G06F11/1064

摘要： One embodiment of the present invention provides a system that fixes bit errors encountered during references to a cache memory. During execution of an application, the system performs a reference to the cache memory by retrieving a data item and an associated error-correcting code from the cache memory. Next, the system computes an error-correcting code from the retrieved data item and compares the computed error-correcting code with the associated error-correcting code. If the computed error-correcting code does not match the associated error-correcting code a bit error has occurred. In this case, the system stores an identifier for the reference in a register within a set of one or more registers associated with the cache memory, so that the bit error can be fixed at a later time. The system also allows the application to continue executing.