公开(公告)号：US08183602B2

公开(公告)日：2012-05-22

申请号：US12275682

申请日：2008-11-21

申请人： Hideyuki Tabata ,  Eiji Ito ,  Hirofumi Inoue

发明人： Hideyuki Tabata ,  Eiji Ito ,  Hirofumi Inoue

IPC分类号： H01L23/52

CPC分类号： H01L27/2481 ,  G11C13/00 ,  G11C13/0009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

摘要翻译： 非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。 通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔连接到第一或第二线不同的单元阵列层。

公开(公告)号：US08183552B2

公开(公告)日：2012-05-22

申请号：US12540896

申请日：2009-08-13

申请人： Shingo Nakajima ,  Eiji Ito ,  Mitsuhiro Noguchi

发明人： Shingo Nakajima ,  Eiji Ito ,  Mitsuhiro Noguchi

IPC分类号： H01L29/02

CPC分类号： H01L27/24

摘要： A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.

摘要翻译： 一种具有设置在第一绝缘体上并沿第一方向延伸的第一布线层的半导体存储器件和在第一布线层上以柱形形式设置的非易失性存储单元， 元件和可变电阻元件串联连接。 可变电阻元件的电阻值根据施加到其上的电压或电流而变化。 阻挡层设置在存储单元上并且被配置在面内方向上。 导电层设置在阻挡层上并且被配置在面内方向上。 第二绝缘体设置在第一绝缘体上并且覆盖存储单元，阻挡层和导电层的侧表面。 第二布线层设置在导电层上并沿第二方向延伸。

公开(公告)号：US20110147822A1

公开(公告)日：2011-06-23

申请号：US12929894

申请日：2011-02-23

申请人： Kenji Aoyama ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

发明人： Kenji Aoyama ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L29/40114 ,  H01L29/66825

摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

公开(公告)号：US20110006424A1

公开(公告)日：2011-01-13

申请号：US12923309

申请日：2010-09-14

申请人： Eiji Ito ,  Hideyuki Kinoshita ,  Tetsuya Kamigaki ,  Koji Hashimoto

发明人： Eiji Ito ,  Hideyuki Kinoshita ,  Tetsuya Kamigaki ,  Koji Hashimoto

IPC分类号： H01L23/532

CPC分类号： G03F7/0035 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

摘要翻译： 一种制造半导体器件的方法包括在下面的区域上形成以第一间距布置的多个虚拟线图案，形成具有形成在虚拟线图案的长边上的预定掩模部分的第一掩模图案，每个第一掩模图案具有 闭环形状并且围绕每个虚拟线图案，去除虚拟线图案，形成具有第一图案部分的第二掩模图案，该第一图案部分覆盖第一掩模图案的端部和位于相邻的第一掩模图案的端部之间的端部部分 端部，使用第一掩模图案和第二掩模图案作为掩模蚀刻下面的区域，以形成各自位于相邻的预定掩模部分之间的沟槽，并且用预定的材料填充沟槽。

公开(公告)号：US20090134432A1

公开(公告)日：2009-05-28

申请号：US12275682

申请日：2008-11-21

申请人： Hideyuki TABATA ,  Eiji Ito ,  Hirofumi Inoue

发明人： Hideyuki TABATA ,  Eiji Ito ,  Hirofumi Inoue

IPC分类号： H01L29/66 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L27/2481 ,  G11C13/00 ,  G11C13/0009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

摘要翻译： 非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。 通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔连接到第一或第二线不同的单元阵列层。

公开(公告)号：US20090033592A1

公开(公告)日：2009-02-05

申请号：US12036150

申请日：2008-02-22

申请人： Seung-Pil Mun ,  Eiji Ito ,  Luck-Hyun Kim ,  Dae-Young Kim

发明人： Seung-Pil Mun ,  Eiji Ito ,  Luck-Hyun Kim ,  Dae-Young Kim

IPC分类号： G09G3/28

CPC分类号： G09G3/296 ,  G09G2310/066

摘要： A plasma display device including a scan circuit, a plasma display panel, and a plurality of power sources for driving the plasma display panel. The scan circuit is configured to apply scan voltages to scan electrodes of the plasma display panel in order to select light-emitting cells and non-light-emitting cells during an address period. The scan circuit includes a capacitor configured to remove the need to provide a current cut-off switch to prevent undesirable current flowing between the power supplies during the operation of the plasma display.

摘要翻译： 一种等离子体显示装置，包括扫描电路，等离子体显示面板和用于驱动等离子体显示面板的多个电源。 扫描电路被配置为对等离子体显示面板的扫描电极施加扫描电压，以便在寻址周期期间选择发光单元和非发光单元。 扫描电路包括被配置为消除提供电流切断开关以防止在等离子体显示器的操作期间不期望的电流在电源之间流动的需要的电容器。

公开(公告)号：US07225519B2

公开(公告)日：2007-06-05

申请号：US10169935

申请日：2001-11-16

申请人： Yukihito Ichikawa ,  Eiji Ito

发明人： Yukihito Ichikawa ,  Eiji Ito

IPC分类号： B23P11/00

CPC分类号： F16C41/008 ,  B23P19/04 ,  B23P21/00 ,  Y10T29/49764 ,  Y10T29/49826

摘要： An assembling method for assembling an assembly by combining a plurality of mating members with each other, wherein inherent information regarding dimensions of individual members, which is necessary for the combination of members, has been marked on the member surface prior to the start of an assembling process, the information marked on the member is read in the assembling process, and members having a dimension that meets a proper combining condition are selected based on the information. An individual member and inherent information regarding the dimension of members can be handled integrally, when the mating members are combined with each other, members having a dimension that meets a proper combining condition are selected, and when the member is processed so as to correspond to the property thereof, proper processing corresponding to the inherent properties of each member can be performed easily and surely without troublesome work.

摘要翻译： 一种组装方法，用于通过将多个配合构件相互组合来组装组件，其中关于构件组合所必需的各个构件的尺寸的固有信息已经在组装开始之前在构件表面上标记 过程中，在组装过程中读取标记在成员上的信息，并且基于该信息来选择具有满足适当组合条件的维度的成员。 单个构件和关于构件的尺寸的固有信息可以一体地处理，当配合构件相互组合时，选择具有满足适当组合条件的尺寸的构件，并且当构件被处理以对应于 其特性，可以容易且可靠地执行对应于每个构件的固有特性的适当处理而不麻烦地工作。

公开(公告)号：US07172301B2

公开(公告)日：2007-02-06

申请号：US10838403

申请日：2004-05-03

申请人： Eiji Ito

发明人： Eiji Ito

IPC分类号： G02B5/10

CPC分类号： B60R1/02 ,  B29C45/0025 ,  B29D11/00596 ,  B29L2011/0058 ,  G02B5/08

摘要： For an optical reflecting mirror formed by applying injection molding to a plastic material, it is an object of the present invention to suppress warpage or distortion due to molding contraction and provide an optical reflecting mirror such as an axial eccentric a spherical mirror or free curved surface mirror with a highly accurate mirror surface, which is an axial eccentric a spherical mirror or free curved surface mirror formed by applying injection molding to a plastic material, including a rib connected in such a way as to intersect with the body having the mirror surface, formed at least at the outer edge of the mirror surface closest to the maximum curvature part within the mirror surface.

摘要翻译： 对于通过向塑料材料注射成型而形成的光反射镜，本发明的目的是抑制由于模制收缩而引起的翘曲或变形，并提供诸如轴向偏心的球面镜或自由曲面的光学反射镜 具有高度准确的镜面的镜面，其是通过向塑料材料施加注射成型而形成的球面镜或自由曲面镜的轴向偏心镜，其包括以与具有镜面的主体相交的方式连接的肋， 至少在反射镜表面的外边缘处形成，最靠近镜面内的最大曲率部分。

公开(公告)号：US20060234165A1

公开(公告)日：2006-10-19

申请号：US11346237

申请日：2006-02-03

申请人： Tetsuya Kamigaki ,  Eiji Ito ,  Koji Hashimoto ,  Hideyuki Kinoshita

发明人： Tetsuya Kamigaki ,  Eiji Ito ,  Koji Hashimoto ,  Hideyuki Kinoshita

IPC分类号： G03F7/26

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of manufacturing a semiconductor device, comprises forming a first mask pattern on an under-layer region, forming a plurality of dummy-line patterns on the under-layer region, the dummy-line patterns being arranged at a first pitch, forming second mask patterns having mask parts provided on long sides of the dummy-line patterns, removing the dummy-line patterns, and etching the under-layer region by using the first mask pattern and the mask parts as a mask.

公开(公告)号：US06994816B2

公开(公告)日：2006-02-07

申请号：US10486892

申请日：2003-04-11

申请人： Takeyuki Ishii ,  Yuji Asai ,  Eiji Ito

发明人： Takeyuki Ishii ,  Yuji Asai ,  Eiji Ito

IPC分类号： B28B3/20 ,  B28B11/16

CPC分类号： B28B11/165 ,  B26D1/46 ,  B28B11/161 ,  B28B17/00 ,  Y10T83/0207 ,  Y10T83/2022

摘要： An apparatus for producing a honeycomb structure having an extruder, at least one cradle and a cutting device comprising a small-gage wire for cutting the honeycomb structure and a notching member; said cradle is provided with a means capable of moving the honeycomb structure extruded from the extruder in the lengthwise direction of the honeycomb structure at nearly the same speed as the extrusion speed of the honeycomb structure, said cutting device is constructed so that the cutting small-gage wire is moved to the honeycomb structure side on the same plane as the plane of stretched small-gage wire, a cutting induction groove is formed on the outer peripheral side surface of the honeycomb structure by the notching member, and immediately thereafter the cutting small-gage wire is positioned in the induction groove, and the cutting small-gage wire is pressed into the honeycomb structure to cut the honeycomb structure.

摘要翻译： 一种具有挤出机，至少一个支架和切割装置的蜂窝结构体的制造装置，其特征在于，包括用于切割所述蜂窝结构体的小规格线材和切口部件; 所述支架设置有能够以与蜂窝结构体的挤出速度几乎相同的速度移动从挤出机沿蜂窝结构体的长度方向挤出的蜂窝结构体的装置，所述切割装置被构造成使得切割小 - 将规格导线移动到与拉伸小规格线的平面相同的平面上的蜂窝结构侧，通过开槽部件在蜂窝结构体的外周侧面上形成切割感应槽，然后切断小 将电线定位在感应槽中，并将切割小规格的电线压入蜂窝结构体中以切割蜂窝结构体。