-
公开(公告)号：US20220303740A1
公开(公告)日：2022-09-22
申请号：US17836931
申请日：2022-06-09
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm
IPC: H04W4/44 , G06F15/173 , H04L67/12 , H04B1/38
Abstract: Apparatuses, systems, and methods related to memory pooling between selected memory resources on vehicles or base stations are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a wireless base station coupled to a first processor coupled to a first memory resource that are configured to enable formation of a memory pool to share data between the first memory resource and a second memory resource at a vehicle responsive to a request to access the second memory resource from the first processor transmitted via the base station. The data shared by the second memory resource is determined to enable performance of a particular functionality, stored by the first memory resource, as at least part of a mission profile for transit of the vehicle.
-
公开(公告)号：US11436082B2
公开(公告)日：2022-09-06
申请号：US17152036
申请日：2021-01-19
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.
-
公开(公告)号：US11422713B2
公开(公告)日：2022-08-23
申请号：US17157797
申请日：2021-01-25
Applicant: Micron Technology, Inc.
Inventor： Erika Prosser , Aaron P. Boehm , Debra M. Bell
Abstract: Methods, systems, and devices for a memory error indicator related to high-reliability applications are described. A memory device may perform error detection procedures to monitor trends in the quantity of bit errors as an indication of the health of the memory device. A memory device may perform error detection procedures concurrently with refresh procedures to detect a quantity of errors (e.g., in a memory array) without degrading the performance of the device or the memory array. The memory device may compare a quantity of errors detected (e.g., in the memory array) with one or more previously detected quantities of errors to determine one or more differences in the quantities of errors. The memory device may generate an error metric based on the differences, and may determine whether the error metric satisfies a threshold. The memory device may output a status indicator (e.g., to a host device) based on whether the error metric satisfies the threshold.
-
公开(公告)号：US20220225068A1
公开(公告)日：2022-07-14
申请号：US17708781
申请日：2022-03-30
Applicant: Micron Technology, Inc.
Inventor： Fa-Long Luo , Glen E. Hush , Aaron P. Boehm
Abstract: Methods, apparatuses, and systems related to wireless main memory for computing are described. A device may include a processor that is wirelessly coupled to a memory array, which may be in a physically separate device. The processor may execute instructions stored in and wirelessly communicated from the memory array. The processor may read data from or write data to the memory array via a wireless communication link (e.g., using resources of an ultra high frequency, super high frequency, and/or extremely high frequency band). Several devices may have a small amount of local memory (or no local memory) and may share, via a wireless communication link, a main memory array. Memory devices may include memory resources and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).
-
公开(公告)号：US20220147419A1
公开(公告)日：2022-05-12
申请号：US17580284
申请日：2022-01-20
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.
-
Patent Agency Ranking
公开(公告)号：US20220129185A1
公开(公告)日：2022-04-28
申请号：US17518164
申请日：2021-11-03
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Debra M. Bell
Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.
-
公开(公告)号：US11294766B2
公开(公告)日：2022-04-05
申请号：US16940783
申请日：2020-07-28
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device indicates, to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on a result of the comparison, an indication of whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, to manage data storage in the memory device, or both.
-
公开(公告)号：US20220100427A1
公开(公告)日：2022-03-31
申请号：US17464333
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Todd Jackson Plum , Scott D. Van De Graaff , Scott E. Scheafer , Mark D. Ingram
IPC: G06F3/06
Abstract: Methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more temperature ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.
-
公开(公告)号：US11269648B2
公开(公告)日：2022-03-08
申请号：US17065749
申请日：2020-10-08
Applicant: Micron Technology, Inc.
Inventor： Glen E. Hush , Aaron P. Boehm , Fa-Long Luo
Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.
-
公开(公告)号：US20220057945A1
公开(公告)日：2022-02-24
申请号：US17396528
申请日：2021-08-06
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Lance W. Dover , Steffen Buch
IPC: G06F3/06
Abstract: Methods, systems, and devices for security techniques for low power state of memory device are described. A host device may initiate a low power state of a memory device. The host device may store a first value of a counter associated with the memory device operating in the low power state and transmit a command to the memory device to enter the low power state. The memory device may increment the counter based on receiving the command and increment the counter to a second value. The host device may validate the memory device based on a difference between the first value of the counter stored by the host device and the second value of the counter.
-
-
-
-
-
-
-
-
-
Search Results
206
records
(took 0.025 seconds)
