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    Phase-locked loop circuit with a mixed mode loop filter
    82.
    发明授权
    Phase-locked loop circuit with a mixed mode loop filter 失效
    具有混合模式环路滤波器的锁相环电路

    公开(公告)号：US07733985B2

    公开(公告)日：2010-06-08

    申请号：US11354764

    申请日：2006-02-14

    申请人： Chih-Chiang Chang

    发明人： Chih-Chiang Chang

    IPC分类号： H03D3/24 ,  H03D3/18

    CPC分类号： H03L7/093

    摘要： A phase-locked loop circuit includes a phase and frequency detector receiving a reference signal and an output signal of the phase-locked loop circuit for generating a detected signal representing a frequency or phase difference therebetween. A digital charge pump coupled to the phase and frequency detector generates a charge control signal in response to the detected signal. A mixed mode loop filter coupled to the digital charge pump filters the charge control signal and generates an oscillation control signal. A voltage controlled oscillator is coupled to the mixed mode loop filter for generating the output signal of the phase-locked loop circuit by adjusting its oscillation frequency in response to the oscillation control signal. The mixed mode loop filter has both digital and analog characteristics in carrying out filtering the charge control signal, thereby reducing a layout area for the same to be implemented on a semiconductor substrate.

    摘要翻译： 锁相环电路包括相位和频率检测器，其接收参考信号和锁相环电路的输出信号，用于产生表示其间的频率或相位差的检测信号。 耦合到相位和频率检测器的数字电荷泵响应于检测到的信号产生充电控制信号。 耦合到数字电荷泵的混合模式环路滤波器对充电控制信号进行滤波并产生振荡控制信号。 压控振荡器耦合到混合模式环路滤波器，用于通过响应于振荡控制信号调整其振荡频率来产生锁相环电路的输出信号。 混合模式环路滤波器在进行充电控制信号的滤波时具有数字和模拟特性，从而减少了要在半导体衬底上实现的布局面积。

    NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT
    83.
    发明申请
    NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT 审中-公开
    性能增强的新型布局架构

    公开(公告)号：US20100127333A1

    公开(公告)日：2010-05-27

    申请号：US12276172

    申请日：2008-11-21

    申请人： Yung-Chin Hou ,  Ta-Pen Guo ,  Harry Chuang ,  Carlos H. Diaz ,  Lee-Chung Lu ,  Li-Chun Tien ,  Oscar M. K. Law ,  Chih-Chiang Chang ,  Chun-Hui Tai ,  Jonathan Lee

    发明人： Yung-Chin Hou ,  Ta-Pen Guo ,  Harry Chuang ,  Carlos H. Diaz ,  Lee-Chung Lu ,  Li-Chun Tien ,  Oscar M. K. Law ,  Chih-Chiang Chang ,  Chun-Hui Tai ,  Jonathan Lee

    IPC分类号： H01L27/092 ,  H01L27/088

    CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823481

    摘要： The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.

    摘要翻译： 本发明提供集成电路。 集成电路包括半导体衬底中的有源区; 设置在有源区中的第一场效应晶体管（FET） 以及设置在有源区域中的隔离结构。 FET包括第一栅极; 形成在所述有源区中并且从第一侧设置在与所述第一栅极相邻的第一区域上的第一源极; 以及形成在所述有源区中并且从第二侧设置在与所述第一栅极相邻的第二区域上的第一漏极。 隔离结构包括邻近第一漏极设置的隔离栅极; 以及隔离源，形成在所述有源区中并邻近所述隔离栅设置，使得所述隔离源和所述第一漏极位于所述隔离栅极的不同侧上。

    KEYBOARD STRUCTURE AND ELECTRONIC DEVICE USING THE SAME
    86.
    发明申请
    KEYBOARD STRUCTURE AND ELECTRONIC DEVICE USING THE SAME 失效
    键盘结构和使用该键盘的电子设备

    公开(公告)号：US20090289817A1

    公开(公告)日：2009-11-26

    申请号：US12467377

    申请日：2009-05-18

    申请人： Zheng Shi ,  Chih-Chiang Chang

    发明人： Zheng Shi ,  Chih-Chiang Chang

    IPC分类号： H03M11/02 ,  G06F3/02

    CPC分类号： H01H13/86 ,  H01H2223/034 ,  H01H2223/056 ,  H01H2231/022

    摘要： A keyboard structure, comprises a housing having at least one post, a key assembly, and at least one connecting portion comprising a ring, the ring coils around the post to connect the key assembly to the housing. The invention also discloses an electronic device using the keyboard structure.

    摘要翻译： 键盘结构包括具有至少一个柱，键组件和包括环的至少一个连接部分的壳体，所述环绕所述柱线圈将所述键组件连接到所述壳体。 本发明还公开了一种使用键盘结构的电子设备。

    SLIDING MECHANISM AND PORTABLE ELECTRONIC DEVICE HAVING THE SAME
    87.
    发明申请
    SLIDING MECHANISM AND PORTABLE ELECTRONIC DEVICE HAVING THE SAME 失效
    具有其滑动机构和便携式电子设备

    公开(公告)号：US20090264167A1

    公开(公告)日：2009-10-22

    申请号：US12146565

    申请日：2008-06-26

    申请人： Zheng Shi ,  Chih-Chiang Chang

    发明人： Zheng Shi ,  Chih-Chiang Chang

    IPC分类号： H04M1/00

    CPC分类号： H04M1/0247 ,  H04M1/0237

    摘要： A sliding mechanism (40) includes a base plate (42), a first sliding plate (44), as second sliding plate (46), and a elastic element (48). The first sliding plate (44) is slidably mounted on the first sliding plate (44) and located adjacent to one side of the base plate (42). The second sliding plate (46) is slidably mounted on the second sliding plate (46) and located adjacent to an opposite side of the base plate (42). The elastic element (48) provides force for driving the first sliding plate (44) and the second sliding plate (46) to slide relative to the base plate (42) and in opposite directions.

    摘要翻译： 滑动机构（40）包括基板（42），第一滑动板（44），第二滑动板（46）和弹性元件（48）。 第一滑动板（44）可滑动地安装在第一滑动板（44）上并且邻近基板（42）的一侧定位。 第二滑动板（46）可滑动地安装在第二滑动板（46）上并且位于邻近基板（42）的相对侧。 弹性元件（48）提供用于驱动第一滑动板（44）和第二滑动板（46）相对于基板（42）和相反方向滑动的力。

    Method for designing phase-lock loop circuits
    89.
    发明授权
    Method for designing phase-lock loop circuits 有权
    设计锁相环电路的方法

    公开(公告)号：US07464346B2

    公开(公告)日：2008-12-09

    申请号：US11472199

    申请日：2006-06-20

    申请人： Mu-Jen Huang ,  Chien-Hung Chen ,  Chih-Chiang Chang

    发明人： Mu-Jen Huang ,  Chien-Hung Chen ,  Chih-Chiang Chang

    IPC分类号： G06F17/50

    CPC分类号： H03L7/00

    摘要： A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.

    摘要翻译： 公开了一种用于设计锁相环（PLL）电路的方法。 该方法包括以下步骤。 提供了第一组知识产权，其中每个都代表在半导体衬底上实现的控制电路。 提供了第二组知识产权，其中每一个代表在半导体衬底上实现的滤波器。 基于PLL电路的预定规格，从第一和第二组中选择智能属性。 所选择的知识产权被集成为代表PLL电路的综合知识产权，使得基于预定规范配置通过使用集成知识产权实现的PLL电路的布局区域。

    Method for designing phase-lock loop circuits
    90.
    发明申请
    Method for designing phase-lock loop circuits 有权

    公开(公告)号：US20080007348A1

    公开(公告)日：2008-01-10

    申请号：US11472199

    申请日：2006-06-20

    申请人： Mu-Jen Huang ,  Chien-Hung Chen ,  Chih-Chiang Chang

    发明人： Mu-Jen Huang ,  Chien-Hung Chen ,  Chih-Chiang Chang

    IPC分类号： H03L7/00

    CPC分类号： H03L7/00

    摘要： A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.