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    Integrated circuit design using DFM-enhanced architecture
    1.
    发明授权
    Integrated circuit design using DFM-enhanced architecture 有权
    采用DFM增强架构的集成电路设计

    公开(公告)号：US08631366B2

    公开(公告)日：2014-01-14

    申请号：US12708242

    申请日：2010-02-18

    Applicant: Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    Inventor： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

    Abstract translation: 集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。 第一标准细胞和第二标准细胞具有相同的细胞变体。 第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。 第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

    Standard Cell without OD Space Effect in Y-Direction
    2.
    发明申请
    Standard Cell without OD Space Effect in Y-Direction 有权
    标准电池在Y方向没有OD空间效应

    公开(公告)号：US20100078725A1

    公开(公告)日：2010-04-01

    申请号：US12345372

    申请日：2008-12-29

    Applicant: Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    Inventor： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    IPC: H01L27/088 ,  H01L29/06

    CPC classification number: H01L27/0207 ,  H01L27/11807

    Abstract: An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

    Abstract translation: 集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。 栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。 第一间隔棒位于半导体衬底中并与第一有源区连接。 第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。 第二间隔杆位于半导体衬底中并连接到第二有源区。 第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

    Mother/daughter switch design with self power-up control
    3.
    发明申请
    Mother/daughter switch design with self power-up control 有权
    母/子开关设计具有自上电控制功能

    公开(公告)号：US20080270813A1

    公开(公告)日：2008-10-30

    申请号：US11789721

    申请日：2007-04-24

    Applicant: Shih-Hsien Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Chun-Hui Tai ,  Cliff Hou

    Inventor： Shih-Hsien Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Chun-Hui Tai ,  Cliff Hou

    IPC: G06F1/32

    CPC classification number: G06F1/3203

    Abstract: System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.

    Abstract translation: 为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。 优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路以及耦合到电路块和第二控制电路的母电路。 在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。 当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。 此外，可以使用旁路电路来减少泄漏电流。

    Reverse-biased PN diode decoupling capacitor
    4.
    发明申请
    Reverse-biased PN diode decoupling capacitor 有权
    反向偏置PN二极管去耦电容

    公开(公告)号：US20080122036A1

    公开(公告)日：2008-05-29

    申请号：US11502094

    申请日：2006-08-10

    Applicant: Hsien-Te Chen ,  Jen-Hang Yang ,  Chun-Hui Tai

    Inventor： Hsien-Te Chen ,  Jen-Hang Yang ,  Chun-Hui Tai

    IPC: H01L29/93

    CPC classification number: H01L29/8611 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0814

    Abstract: This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.

    Abstract translation: 本发明公开了一种集成电路中的去耦电容器，其包括多个专用PN二极管，其总结面积大于专用PN二极管旨在保护的功能器件的总有效面积的十分之一，N型 耦合到正电源电压（Vdd）的专用PN二极管的区域和耦合到互补的较低电源电压（Vss）的专用PN二极管的P型区域，其中专用PN二极管被反向偏置。

    Standard cell without OD space effect in Y-direction
    6.
    发明授权
    Standard cell without OD space effect in Y-direction 有权
    标准电池在Y方向没有OD空间效应

    公开(公告)号：US07808051B2

    公开(公告)日：2010-10-05

    申请号：US12345372

    申请日：2008-12-29

    Applicant: Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    Inventor： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    IPC: H01L29/76

    CPC classification number: H01L27/0207 ,  H01L27/11807

    Abstract: An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

    Abstract translation: 集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。 栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。 第一间隔棒位于半导体衬底中并与第一有源区连接。 第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。 第二间隔杆位于半导体衬底中并连接到第二有源区。 第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

    Voltage level shifter with single well voltage
    8.
    发明申请
    Voltage level shifter with single well voltage 有权
    具有单井电压的电压电平转换器

    公开(公告)号：US20080143418A1

    公开(公告)日：2008-06-19

    申请号：US11639006

    申请日：2006-12-14

    Applicant: Lee-Chung Lu ,  Chung-Hsing Wang ,  Chun-Hui Tai ,  Li-Chun Tien ,  Shun-Li Chen

    Inventor： Lee-Chung Lu ,  Chung-Hsing Wang ,  Chun-Hui Tai ,  Li-Chun Tien ,  Shun-Li Chen

    IPC: H03L5/00

    CPC classification number: H03K3/35613

    Abstract: This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

    Abstract translation: 本发明公开了一种电压电平转换器，它包括具有栅极，源极和体耦合到输入端的第一P型金属氧化物半导体（PMOS）晶体管，第一正电压电源和第二正电压 电源，以及分别具有源极，漏极和体耦合到第三正电压电源，输出节点和第二正电压电源的第二PMOS晶体管，其中形成第一和第二PMOS晶体管 在一个Nwell。

    Variable layout design for multiple voltage applications
    9.
    发明授权
    Variable layout design for multiple voltage applications 有权
    多电压应用的可变布局设计

    公开(公告)号：US06903389B1

    公开(公告)日：2005-06-07

    申请号：US10868606

    申请日：2004-06-15

    Applicant: Chun-Hui Tai ,  Li-Chun Tien

    Inventor： Chun-Hui Tai ,  Li-Chun Tien

    IPC: H01L27/02 ,  H01L27/10 ,  H01L27/118

    CPC classification number: H01L27/11807 ,  H01L27/0207

    Abstract: An integrated circuit it comprises a logic cell. The logic cell is without nwell contacts and comprises top and bottom voltage supply wires. The integrated circuit also comprises a first filler cell comprising top and d bottom voltage supply wires and an nwell region coupled to the bottom voltage supply wire. The integrated circuit further comprises a second filler cell with an nwell region coupled to a top voltage supply wire. The integrated circuit still further comprises a third filler cell comprising top and bottom voltage supply wires. The third filler cell also comprising a pair of nwell regions. One of nwell regions is coupled to the top voltage supply wire and the other nwell region is coupled to the bottom voltage supply wire. The standard cell and the filler cells each comprise a PRboundary overlapping a top portion of the nwell region in each cell by a first distance.

    Abstract translation: 其集成电路包括逻辑单元。 逻辑单元没有nwell触点，并且包括顶部和底部电压电源线。 集成电路还包括第一填充单元，其包括顶部和底部电压电源线以及耦合到底部电压电源线的nwell区域。 集成电路还包括具有耦合到顶部电压电源线的nwell区域的第二填充单元。 集成电路还包括包括顶部和底部电压电源线的第三填充单元。 第三填充单元还包括一对nwell区域。 n个区域中的一个耦合到顶部电压电源线，另一个nwell区域耦合到底部电压电源线。 标准单元和填充单元每个都包括与每个单元格中的nwell区域的顶部重叠第一距离的PR边界。

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