公开(公告)号：US08688844B1

公开(公告)日：2014-04-01

申请号：US13460392

申请日：2012-04-30

Applicant: Mark Stuart Day ,  Brian Miller ,  Nitin Gupta ,  Alfred Landrum ,  Blanco Zee Leung Lam

Inventor： Mark Stuart Day ,  Brian Miller ,  Nitin Gupta ,  Alfred Landrum ,  Blanco Zee Leung Lam

IPC: G06F15/16 ,  G06F12/00

CPC classification number: H04L67/141 ,  H04L29/08792 ,  H04L41/00 ,  H04L63/0254 ,  H04L63/029 ,  H04L63/164 ,  H04L67/2876 ,  H04L69/04 ,  H04L69/14 ,  H04L69/163 ,  H04W80/06

Abstract: Transparent network devices intercept messages from non-transparent network devices that establish a connection. Transparent network devices modify these messages to establish an inner connection with each other. The transparent network devices mimic at least some of the outer connection messages to establish their inner connection. The mimicked messages and any optional reset messages are intercepted by the transparent network devices to prevent them from reaching the outer connections. Transparent network devices modify network traffic, using error detection data, fragmentation data, or timestamps, so that inner connection network traffic inadvertently received by outer connection devices is rejected or ignored by the outer connection network devices. Transparent network devices may use different sequence windows for inner and outer connection network traffic. To prevent overlapping sequence windows, transparent network devices monitor the locations of the inner and outer connection sequence windows and may rapidly advance the inner connection sequence window as needed.

Abstract translation: 透明网络设备拦截来自建立连接的不透明网络设备的消息。 透明网络设备修改这些消息以建立彼此的内部连接。 透明网络设备模拟至少一些外部连接消息以建立其内部连接。 模拟消息和任何可选的重置消息被透明网络设备拦截，以防止它们到达外部连接。 透明网络设备修改网络流量，使用错误检测数据，碎片数据或时间戳，使外部连接设备无意中接收的内部连接网络流量被外部连接网络设备拒绝或忽略。 透明网络设备可以对内部和外部连接网络流量使用不同的序列窗口。 为了防止重叠序列窗口，透明网络设备监视内部和外部连接序列窗口的位置，并可根据需要快速推进内部连接顺序窗口。

公开(公告)号：US08639447B2

公开(公告)日：2014-01-28

申请号：US12602481

申请日：2008-06-02

Applicant: Sangtae Kim ,  Nitin Gupta ,  Pavel A. Pevzner

Inventor： Sangtae Kim ,  Nitin Gupta ,  Pavel A. Pevzner

IPC: G01N33/48 ,  G01N31/00 ,  G06F7/60 ,  G06F19/22 ,  G06F19/12

CPC classification number: G06F19/22 ,  G01N33/6848 ,  G06F19/12 ,  G06F19/18 ,  H01J49/0036

Abstract: A method for identifying peptides using tandem mass spectrometry takes the spectrum for a peptide to be analyzed and uses a scoring function to score a match between the spectrum and each candidate peptide in a peptide database. The scoring function has a value corresponding to a number of fragment peaks in the spectrum that match fragment peaks in a spectrum of the candidate peptide. Using the match scores, a generating function of the spectrum is computed to determine the number of peptide reconstructions at each value of the scoring function. The generating function is then used to determine the number of candidate peptides for each match score and the probability of a peptide having a given match score to the spectrum. A spectral probability can be determined by calculating the total probability of all peptides with scores equal to or larger than the given match score.

Abstract translation: 使用串联质谱法鉴定肽的方法取得待分析肽的光谱，并使用评分函数对肽数据库中的光谱和每个候选肽之间的匹配进行评分。 评分函数具有对应于与候选肽的谱中的片段峰匹配的谱中的片段峰数的值。 使用匹配分数，计算光谱的生成函数，以确定在评分函数的每个值处的肽重构的数量。 然后使用生成函数来确定每个匹配得分的候选肽的数目和具有给定匹配得分的肽对于该光谱的概率。 可以通过计算具有等于或大于给定匹配分数的分数的所有肽的总概率来确定光谱概率。

公开(公告)号：US20130297855A1

公开(公告)日：2013-11-07

申请号：US13464714

申请日：2012-05-04

Applicant: Nitin Gupta ,  Kiron Vijayasankar ,  Joshua Berry

Inventor： Nitin Gupta ,  Kiron Vijayasankar ,  Joshua Berry

IPC: G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0619 ,  G06F3/0685 ,  G06F11/1441 ,  G06F11/1471 ,  G06F2201/82

Abstract: Relatively small capacity solid-state storage devices (SSD) are combined with larger capacity magnetic disk storage devices for storing storage block write data to ensure data consistency. Write operations are stored in a sequential write buffer in an SSD to guarantee the storage of write data and then copied from the sequential write buffer to the destination address in a magnetic disk storage device. The sequential write buffer store write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the magnetic disk storage device in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, the most recent value of the checkpoint index is retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage device.

Abstract translation: 相对较小容量的固态存储设备（SSD）与更大容量的磁盘存储设备相结合，用于存储存储块写数据，以确保数据一致性。 写入操作存储在SSD中的顺序写入缓冲器中，以保证写入数据的存储，然后从顺序写入缓冲器复制到磁盘存储设备中的目标地址。 顺序写入缓冲器将写入数据写入对应于写入操作的接收顺序的位置。 从顺序写入缓冲器写入的数据以相同的顺序被传送到磁盘存储设备，并且检查点索引被频繁更新以指示某些传输的完成。 在系统初始化期间，检索点索引的最新值被检索并用作将写入数据从顺序写入缓冲器传送到磁盘存储设备的起始位置。

公开(公告)号：US20130297854A1

公开(公告)日：2013-11-07

申请号：US13464713

申请日：2012-05-04

Applicant: Nitin Gupta ,  Kiron Vijayasankar ,  Joshua Berry

Inventor： Nitin Gupta ,  Kiron Vijayasankar ,  Joshua Berry

IPC: G06F12/02

CPC classification number: G06F11/1441 ,  G06F11/1471 ,  G06F2201/82

Abstract: Solid-state storage devices (SSD) are combined with larger capacity magnetic disk-based RAID arrays for storing write data to ensure data consistency across multiple RAID disks. Write operations are stored in a sequential write buffer in at least one SSD to guarantee their storage and then copied from the sequential write buffer to the destination address in RAID array. The sequential write buffer stores write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the RAID array in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, a copy of the sequential write buffer and its associated checkpoint index are retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage devices in the RAID array.

Abstract translation: 固态存储设备（SSD）与更大容量的基于磁盘的RAID阵列相结合，用于存储写入数据，以确保多个RAID磁盘之间的数据一致性。 写入操作存储在至少一个SSD中的顺序写入缓冲器中，以保证其存储，然后从顺序写缓冲区复制到RAID阵列中的目标地址。 顺序写入缓冲器将写入数据存储在与写入操作的接收顺序相对应的位置。 将顺序写入缓冲区中的写入数据以相同的顺序传输到RAID阵列，并且检查点索引经常更新以指示某些传输的完成。 在系统初始化期间，检索顺序写入缓冲器及其关联的检查点索引的副本，并将其用作将写入数据从顺序写入缓冲区传送到RAID阵列中的磁盘存储设备的起始位置。

公开(公告)号：US08462624B2

公开(公告)日：2013-06-11

申请号：US11494025

申请日：2006-07-26

Applicant: Steve McCanne ,  Nitin Gupta

Inventor： Steve McCanne ,  Nitin Gupta

IPC: H04L12/26

CPC classification number: H04L47/10 ,  H04L1/0002 ,  H04L1/004 ,  H04L1/0057 ,  H04L1/1809 ,  H04L1/187 ,  H04L1/188 ,  H04L43/0835 ,  H04L43/0847 ,  H04L47/11 ,  H04L47/25 ,  H04L47/27

Abstract: A network stack includes a packet loss analyzer that distinguishes between packet losses due to congestion and due to lossyness of network connections. The loss analyzer observes the packet loss patterns for comparison with a packet loss model. The packet loss model may be based on a Forward Error Correction (FEC) system. The loss analyzer determines if lost packets could have been recovered by a receiving network device, if FEC had been used. If the lost packets could have been corrected by FEC, the loss analyzer assumes that no network congestion exists and that the packet loss comes from the lossy aspects of the network, such as radio interference for wireless networks. If the loss analyzer determines that some of the lost packet could not have been recovered by the receiving network device, the loss analyzer assumes that network congestion causes these packet losses and reduces the data rate.

Abstract translation: 网络堆栈包括分组丢失分析器，其区分由于拥塞引起的分组丢失以及由于网络连接的有损性。 损耗分析仪观察丢包模式，以便与丢包模型进行比较。 分组丢失模型可以基于前向纠错（FEC）系统。 如果使用了FEC，丢失分析器将确定丢失的数据包是否已被接收网络设备恢复。 如果丢失的分组可能被FEC纠正，则丢失分析器假设没有网络拥塞，并且分组丢失来自网络的有损方面，例如无线网络的无线电干扰。 如果丢失分析器确定某些丢失的分组不能被接收网络设备恢复，则丢失分析器假设网络拥塞导致这些分组丢失并降低数据速率。

公开(公告)号：US08457628B2

公开(公告)日：2013-06-04

申请号：US13461660

申请日：2012-05-01

Applicant: Jaya L Jeyaseelan ,  Nitin Gupta

Inventor： Jaya L Jeyaseelan ,  Nitin Gupta

IPC: H04W4/00

CPC classification number: H04W8/02 ,  H04W36/30

Abstract: A mobile station in a wireless network includes a roaming timer. The roaming timer is set based on various criteria, and when the roaming timer expires, an attempt to roam is performed.

Abstract translation: 无线网络中的移动台包括漫游定时器。 基于各种标准设置漫游定时器，并且当漫游定时器到期时，执行漫游尝试。

公开(公告)号：US08378740B2

公开(公告)日：2013-02-19

申请号：US12980724

申请日：2010-12-29

Applicant: Nitin Gupta

Inventor： Nitin Gupta

IPC: G05F1/10

CPC classification number: H03K19/018507 ,  H03K19/00384

Abstract: A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage.

Abstract translation: 开关电路包括具有输入端，输出端，第一源极端子，偏置端子和第二源极端子的源极跟随器电流镜; 耦合到电流镜的输入的电流源; 耦合到电流镜的输出的输出端; 耦合到所述第一源极的第一偏置晶体管; 耦合到电流镜的偏置端子的第二偏置晶体管; 以及耦合到第二源极端子的驱动器晶体管。 电流镜中的输入晶体管的尺寸使得输入电压基本上与电源电压无关。

公开(公告)号：US08237483B2

公开(公告)日：2012-08-07

申请号：US12982593

申请日：2010-12-30

Applicant: Nitin Gupta ,  Nitin Jain

Inventor： Nitin Gupta ,  Nitin Jain

IPC: H03K3/00

CPC classification number: H03K5/151 ,  H03K2005/00136

Abstract: A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.

Abstract translation: 一种用于处理包括不同极性的第一和第二时钟沿的时钟信号的电路，所述电路包括用于反相第一时钟沿以产生反相第一时钟沿的反相器，并且反相第二时钟沿以产生反相第二时钟沿; 第一通路门，用于接收反相时钟沿并输出第一极性的第一触发信号; 以及第二通路门，用于接收第二时钟沿并输出第一极性的第二触发信号，其中第二通道门被控制为响应于反相的第二时钟沿打开; 由此第一时钟沿和第一触发信号之间的延迟基本上等于第二时钟沿和第二触发信号之间的延迟。

公开(公告)号：US08183911B2

公开(公告)日：2012-05-22

申请号：US12581578

申请日：2009-10-19

Applicant: Somnath Kundu ,  Pikul Sarkar ,  Nitin Gupta

Inventor： Somnath Kundu ,  Pikul Sarkar ,  Nitin Gupta

IPC: G11C5/14

CPC classification number: H03K17/00 ,  H03K17/0822

Abstract: An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.

Abstract translation: 集成电路包括多个焊盘。 集成电路还包括具有到第一个焊盘的开漏连接的共源共栅晶体管。 集成电路中包含偏置发生器电路。 偏置发生器电路具有连接到共源共栅晶体管的栅极端子的输出。 在第一操作模式中，偏置发生器输出偏置信号，该偏置信号是从存在于第二焊盘处的集成电路电源电压导出的。 然而，在不存在集成电路电源电压时提供的第二操作模式中，偏置发生器产生从存在于第一焊盘处的电压导出的偏置信号。

公开(公告)号：US20120099832A1

公开(公告)日：2012-04-26

申请号：US12908714

申请日：2010-10-20

Applicant: Nitin Gupta ,  Tapas Nandy

Inventor： Nitin Gupta ,  Tapas Nandy

IPC: H04N5/775 ,  H04N5/765

CPC classification number: G11B27/105 ,  H04N5/907

Abstract: A portable video player includes: a data input coupled to a memory module to store at least one video file, a video decoder coupled to the memory module via a memory interface to decode the video file, and a video interface connector to output to a display the decoded video file.

Abstract translation: 便携式视频播放器包括：耦合到存储器模块以存储至少一个视频文件的数据输入，经由存储器接口耦合到存储器模块以解码视频文件的视频解码器，以及视频接口连接器以输出到显示器 解码的视频文件。