-
81.发明授权Single chip integrated circuit distributed shared memory (DSM) and communications nodes 失效单芯片集成电路分布式共享存储器（DSM）和通信节点
公开(公告)号：US5963975A
公开(公告)日：1999-10-05
申请号：US932042
申请日：1997-09-17
CPC分类号： G06F12/0817
摘要： The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed. The RISC processor is substantially smaller than a more complicated processor that would be required to provide the same processing speed in a multi-chip DSM implementation, thereby enabling the RISC processor to fit on the chip with the other elements. A single-chip communications node that can be used in telecommunications networks other than DSM includes a memory controller for providing local and remote memory coherency, and a bidirectional interconnect unit that converts memory access instructions into memory access messages and vice-versa.
摘要翻译： 高速缓冲存储器的容量比多芯片分布式共享存储器（DSM）实现所需的容量大大减少，以使得高速缓冲存储器，主存储器，处理器和必需的逻辑和控制电路能够安装在单个集成电路芯片 。 由降低的高速缓存存储器容量创建的增加的高速缓存未命中率由通过在单个芯片上集成主存储器和处理器而减少的高速缓存未命中分辨率周期来补偿。 减小的高速缓存未命中分辨率周期使得处理器时钟速率能够显着增加，使得可以利用具有简单功能的处理器，诸如精简指令集计算机（RISC）处理器，并且仍然提供所需的处理速度。 RISC处理器远小于在多芯片DSM实现中提供相同处理速度所需的更复杂的处理器，从而使RISC处理器能够与其他元件相配合。 可以用于DSM以外的电信网络中的单芯片通信节点包括用于提供本地和远程存储器一致性的存储器控制器，以及将存储器访问指令转换为存储器访问消息的反向互连的双向互连单元。
-
82.发明授权Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows 失效一种集成电路芯片的电池放置方法，包括混沌放置和移动窗口
公开(公告)号：US5903461A
公开(公告)日：1999-05-11
申请号：US862791
申请日：1997-05-23
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译： 在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。 重组优化过程的结果以产生优化的细胞放置。 分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。 该系统可以应用于初始放置，布线，布局改进等问题。 处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。 或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。 处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。
-
83.发明授权Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement method 失效集成电路物理设计自动化系统优化处理采用混沌健身改进方法
公开(公告)号：US5682322A
公开(公告)日：1997-10-28
申请号：US229949
申请日：1994-04-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The fitness of a cell placement for an integrated circuit chip is optimized by relocating at least some of cells to new locations that provide lower interconnect congestion. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor .lambda.. The value of .lambda. is selected such that the cell relocation operations will cause the placement to converge toward an optimal configuration without chaotic diversion, but with a sufficiently high chaotic element to prevent the optimization operation from becoming stuck at local fitness maxima. The new cell locations can be modified to include the effects of cells in other locations, such as by incorporating a function of cell density gradient or force direction into the computation. This spreads out clumps of cells so that the density of cells is more uniform throughout the placement. The attraction between cells in the nets is balanced against repulsion caused by a high local cell density, providing an optimized tradeoff of wirelength, feasibility and congestion.
摘要翻译： 通过将至少一些单元重定位到提供较低互连拥塞的新位置来优化用于集成电路芯片的单元布局的适应性。 对于每个单元，计算连接单元的单元格网格的质心。 然后，电池向质心移动一个距离，该距离等于从电池的当前位置到质心乘以“混沌”因子λ的距离。 选择λ的值，使得单元重定位操作将导致放置朝向最佳配置收敛而没有混沌转移，但是具有足够高的混沌元素以防止优化操作变得卡在局部适应度最大值。 可以修改新的单元位置以将单元格的效果包括在其他位置，例如通过将单元密度梯度或力方向的函数合并到计算中。 这扩散了细胞团，使得细胞的密度在整个放置期间更均匀。 网络中的细胞之间的吸引力与由局部细胞密度较高引起的排斥平衡，从而提供了线长，可行性和拥塞的最优化折中。
-
84.发明授权Computer implemented method for producing optimized cell placement for integrated circiut chip 失效用于集成循环芯片生产优化的电池放置的计算机实现方法
公开(公告)号：US5636125A
公开(公告)日：1997-06-03
申请号：US559206
申请日：1995-11-13
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译： 在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。 重组优化过程的结果以产生优化的细胞放置。 分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。 该系统可以应用于初始放置，布线，布局改进等问题。 处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。 或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。 处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。
-
85.发明授权
公开(公告)号：US5495419A
公开(公告)日：1996-02-27
申请号：US229826
申请日：1994-04-19
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译： 在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。 重组优化过程的结果以产生优化的细胞放置。 分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。 该系统可以应用于初始放置，布线，布局改进等问题。 处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。 或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。 处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。
-
公开(公告)号：US08132075B2
公开(公告)日：2012-03-06
申请号：US11924385
申请日：2007-10-25
IPC分类号： H03M13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译： 路由复用器系统基于所选择的p个输入的排列来提供p个输出。 多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。 模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。 多个控制位表各自包含基于相应置换的布置中的多个位。 存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。
-
87.发明授权Method and system for outputting a sequence of commands and data described by a flowchart 有权用于输出由流程图描述的命令和数据序列的方法和系统公开(公告)号：US07472358B2
公开(公告)日：2008-12-30
申请号：US11260517
申请日：2005-10-27
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译： 本发明是用于输出由流程图描述的命令和数据序列的方法和系统。 该方法包括以下步骤。 接收描述命令和数据序列的流程图。 流程图包括多个流程图符号。 多个流程图符号中的每一个被分配有ROM（只读存储器）记录。 分配的ROM记录存储在ROM中。 产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。 。 。 xN，并输出命令和数据的顺序。
-
公开(公告)号：US07315993B2
公开(公告)日：2008-01-01
申请号：US10999468
申请日：2004-11-30
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean value 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean value 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译： 本发明提供了一种RRAM拼接网表的验证方法。 该方法可以包括以下步骤。 属性RRAM平铺网表的所有网络和单元格的“memory_number”，“clock_number”和“netlist_part”被设置为0.值为0的布尔值分配给RRAM平铺网表的所有地网，布尔值1 被分配给RRAM平铺网表的所有电网。 对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。 。 。 ，N.
-
89.发明授权System and method for efficiently testing a large random access memory space 失效用于有效测试大型随机存取存储空间的系统和方法公开(公告)号：US07305597B1
公开(公告)日：2007-12-04
申请号：US10646535
申请日：2003-08-22
CPC分类号： G11C29/26 , G11C29/1201 , G11C29/40 , G11C2029/2602 , G11C2029/3602
摘要： A system for, and method of, allowing conventional memory test circuitry to test parallel memory arrays and an integrated circuit incorporating the system or the method. In one embodiment, the system includes: (1) bit pattern distribution circuitry that causes a probe bit pattern generated by the memory test circuitry to be written to each of the memory arrays, (2) a pseudo-memory, coupled to the bit pattern distribution circuitry, that receives a portion of the probe bit pattern and (3) combinatorial logic, coupled to the pseudo-memory, that employs the portion and data-out bit patterns read from the memory arrays to generate a response bit pattern that matches the probe bit pattern only if all of the data-out bit patterns match the probe bit pattern.
摘要翻译： 用于允许传统的存储器测试电路测试并行存储器阵列的系统和方法以及结合该系统或方法的集成电路。 在一个实施例中，系统包括：（1）位图模式分配电路，其使得存储器测试电路产生的探针位模式被写入每个存储器阵列，（2）耦合到位模式的伪存储器 分配电路，其接收探针位模式的一部分和（3）耦合到伪存储器的组合逻辑，其采用从存储器阵列读取的部分和数据输出位模式，以产生与存储器阵列匹配的响应位模式 探针位模式只有当所有数据输出位模式与探头位模式匹配时。
-
90.发明授权Method and BIST architecture for fast memory testing in platform-based integrated circuit 有权方法和BIST架构，用于基于平台的集成电路中的快速内存测试公开(公告)号：US07216278B2
公开(公告)日：2007-05-08
申请号：US10999493
申请日：2004-11-30
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/26 , G11C2029/2602
摘要： The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
摘要翻译： 本发明提供了一种用于基于平台的集成电路中的快速存储器测试的方法和BIST架构。 该方法可以包括以下步骤。 启动Mem-BIST控制器发送器，使用确定性和无条件测试算法为平台中的存储器生成输入信号。 输入信号被第一组管道延迟了n个时钟周期。 延迟的输入信号由存储器接收，并且由存储器产生输出信号。 输出信号被第二个流水线延迟了m个时钟周期。 启动Mem-BIST控制器接收器以接收延迟的输出信号进行比较。
-
-
-
-
-
-
-
-
-
搜索结果
196 条记录 (耗时 0.064 秒)
