公开(公告)号：US07337280B2

公开(公告)日：2008-02-26

申请号：US11055301

申请日：2005-02-10

申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

公开(公告)号：US07200717B2

公开(公告)日：2007-04-03

申请号：US10965144

申请日：2004-10-14

申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F12/0855

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括处理器核心，该处理器核心包括通过存储的上级高速缓存，指令执行指令排序单元，数据寄存器以及耦合到指令排序单元的至少一个指令执行单元， 同时执行多个指令线程。 所述处理器核心响应于所述至少一个指令执行单元在与冲突存储条件相关联的预留危险窗口期间执行在所述存储通过上级高速缓存中的绑定到加载目标地址的第一线程中的加载保留指令 如果第二线程的存储条件操作成功，则第二线程的操作使得第一线程的后续存储条件操作到与加载目标地址匹配的存储目标地址失败。

公开(公告)号：US07055002B2

公开(公告)日：2006-05-30

申请号：US10424486

申请日：2003-04-25

申请人： Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  Kevin Franklin Reick ,  Derek Edward Williams

发明人： Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  Kevin Franklin Reick ,  Derek Edward Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0804 ,  G06F12/0897

摘要： A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the L2 cache to an L3 cache in response to the purge commands, and correcting errors (single-bit) in the cache lines as they are flushed to the L3 cache. Purge commands are issued only when the processor cores associated with the L2 cache have an idle cycle available in a store pipe to the cache. The flush rate of the purge commands can be programmably set, and the purge mechanism can be implemented either in software running on the computer system, or in hardware integrated with the L2 cache. In the case of the software, the purge mechanism can be incorporated into the operating system. In the case of hardware, a purge engine can be provided which advantageously utilizes the store pipe that is provided between the L1 and L2 caches. The L2 cache can be forced to victimize cache lines, by setting tag bits for the cache lines to a value that misses in the L2 cache (e.g., cache-inhibited space). With the eviction mechanism of the cache placed in a direct-mapped mode, the address misses will result in eviction of the cache lines, thereby flushing them to the L3 cache.

摘要翻译： 通过周期性地向L2高速缓存发出一系列清除命令来减少计算机系统（例如，L2高速缓存）的高速缓冲存储器中的错误的方法，响应于清除，将缓存行从L2高速缓存刷新到L3高速缓存 命令和纠正高速缓存行中的错误（单位），因为它们被刷新到L3高速缓存。 清除命令仅在与L2缓存关联的处理器核心具有可用于缓存的存储管道中的空闲周期时发出。 清除命令的刷新速率可以可编程设置，并且清除机制可以在计算机系统上运行的软件中，也可以在与L2缓存集成的硬件中实现。 在软件的情况下，可以将清除机构并入操作系统。 在硬件的情况下，可以提供有利地利用设置在L1和L2高速缓存之间的存储管道的清洗引擎。 通过将高速缓存行的标记位设置为L2高速缓存中缺少的值（例如，禁止高速缓存的空间），L2高速缓存可能被迫使高速缓存行受害。 由于高速缓存的驱逐机制处于直接映射模式，地址未命中将导致高速缓存线的驱逐，从而将它们刷新到L3高速缓存。

公开(公告)号：US06950909B2

公开(公告)日：2005-09-27

申请号：US10424645

申请日：2003-04-28

申请人： Guy Lynn Guthrie ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Derek Edward Williams

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0817

摘要： A cache access mechanism/system for reducing contention in a multi-sectored cache via serialization of overlapping write accesses to different blocks of a cache line to enable accurate cache directory updates. When a first queue issues a write access request for a first block of a cache line, the first queue concurrently asserts a last_in_line signal identifying the first queue as the last sequential queue to request access to that cache line. If there is an active write access requests for the cache line, the first queue undertakes a series of operations to enable sequentially correct updates to the cache directory with all previous updates taken into consideration. Included in these operations are tracking the completion of the write access and the corresponding write to the associated cache directory and copying the cache directory state to be updated from the parent queue (rather than from the cache directory) so that the parent queue's update of the directory state is included (and not overwritten) when the first queue writes to the directory. The correct cache directory state is then stored within the associated cache directory.

摘要翻译： 一种缓存访问机制/系统，用于通过对对高速缓存行的不同块的重叠写访问的串行化来减少多扇区高速缓存中的竞争，以实现精确的高速缓存目录更新。 当第一队列发出针对高速缓存行的第一块的写访问请求时，第一队列同时断定标识第一队列的last_in_line信号作为请求访问该高速缓存行的最后一个顺序队列。 如果存在针对高速缓存行的活动写入访问请求，则第一个队列进行一系列操作，以便能够对所有先前更新进行考虑的顺序更新到缓存目录。 这些操作中包括跟踪写访问的完成和对相关缓存目录的相应写入，并从父队列（而不是从缓存目录）复制要更新的缓存目录状态，以便父队列的更新 当第一个队列写入目录时，包含目录状态（而不是覆盖）。 然后将正确的缓存目录状态存储在关联的高速缓存目录中。

公开(公告)号：US08433851B2

公开(公告)日：2013-04-30

申请号：US11839663

申请日：2007-08-16

申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。

公开(公告)号：US07490202B2

公开(公告)日：2009-02-10

申请号：US11956112

申请日：2007-12-13

申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

公开(公告)号：US20090049248A1

公开(公告)日：2009-02-19

申请号：US11839663

申请日：2007-08-16

申请人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

发明人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。

公开(公告)号：US07454577B2

公开(公告)日：2008-11-18

申请号：US11055476

申请日：2005-02-10

申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

公开(公告)号：US07305523B2

公开(公告)日：2007-12-04

申请号：US11056673

申请日：2005-02-12

申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0831 ,  G06F12/127

摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss.

摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。

公开(公告)号：US07840758B2

公开(公告)日：2010-11-23

申请号：US11689990

申请日：2007-03-22

申请人： Robert H. Bell, Jr. ,  Hugh Shen ,  Jeffrey Adam Stuecheli ,  Derek Edward Williams

发明人： Robert H. Bell, Jr. ,  Hugh Shen ,  Jeffrey Adam Stuecheli ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F12/0897

摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。