利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

120 条记录 (耗时 0.031 秒)

    Processor, data processing system and method for synchronizing access to data in shared memory
    1.
    发明授权
    Processor, data processing system and method for synchronizing access to data in shared memory 有权
    处理器，数据处理系统和方法，用于同步共享存储器中数据的访问

    公开(公告)号：US07228385B2

    公开(公告)日：2007-06-05

    申请号：US10965113

    申请日：2004-10-14

    申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

    发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3851 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0855

    摘要： A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.

    摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括存储器上级缓存器，取指令执行指令排序单元，至少一个执行存储条件指令以确定存储目标地址的指令执行单元，存储器 在存储条件指令的执行之后，缓存与存储队列相关联的对应存储操作，定序器逻辑的队列。 定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响，在存储条件操作的解析之前无效，存储器中的高速缓存行 加载预备操作先前绑定到的高级缓存。

    Reducing Wiring Congestion in a Cache Subsystem Utilizing Sectored Caches with Discontiguous Addressing
    3.
    发明申请
    Reducing Wiring Congestion in a Cache Subsystem Utilizing Sectored Caches with Discontiguous Addressing 失效
    减少使用不连续寻址的扇区高速缓存子系统中的接线拥塞

    公开(公告)号：US20090049248A1

    公开(公告)日：2009-02-19

    申请号：US11839663

    申请日：2007-08-16

    申请人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

    发明人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

    摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

    摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。

    Cache memory direct intervention
    5.
    发明授权
    Cache memory direct intervention 失效
    缓存内存直接干预

    公开(公告)号：US07305523B2

    公开(公告)日：2007-12-04

    申请号：US11056673

    申请日：2005-02-12

    申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

    发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/0831 ,  G06F12/127

    摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss.

    摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。

    System and method of re-ordering store operations within a processor
    6.
    发明授权
    System and method of re-ordering store operations within a processor 失效
    在处理器内重新排序存储操作的系统和方法

    公开(公告)号：US07284102B2

    公开(公告)日：2007-10-16

    申请号：US11054450

    申请日：2005-02-09

    申请人： Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke ,  Derek Edward Williams

    发明人： Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke ,  Derek Edward Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/3824 ,  G06F12/0817

    摘要： A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.

    摘要翻译： 一种用于重新排序从处理器核到存储队列的存储操作的系统和方法。 当存储队列从处理器核心接收到新的处理器发出的存储操作时，存储队列控制器在存储队列中分配新的条目。 响应于在商店队列中分配新条目，商店队列控制器确定新条目是否依赖于商店队列中的至少一个其他有效条目。 响应于确定新条目取决于存储队列中的至少一个其他有效条目，存储队列控制器禁止向RC调度逻辑请求新条目，直到新条目依赖于其上的每个有效条目已经成功 通过RC调度逻辑调度到RC机器。

    Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
    8.
    发明授权
    Data processing system and method for efficient communication utilizing an Tn and Ten coherency states 有权
    数据处理系统和利用Tn和10相​​关性状态的高效通信方法

    公开(公告)号：US07480772B2

    公开(公告)日：2009-01-20

    申请号：US11835984

    申请日：2007-08-08

    申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

    发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

    摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

    摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

    Processor, data processing system and method for synchronzing access to data in shared memory
    9.
    发明授权
    Processor, data processing system and method for synchronzing access to data in shared memory 失效
    处理器，数据处理系统和方法，用于同步共享存储器中数据的访问

    公开(公告)号：US07197604B2

    公开(公告)日：2007-03-27

    申请号：US10965151

    申请日：2004-10-14

    申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

    发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3851

    摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.

    摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。 指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。 处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从 通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。