公开(公告)号：US6145038A

公开(公告)日：2000-11-07

申请号：US833228

申请日：1997-10-31

申请人： Jerry Don Lewis ,  John Steven Dodson ,  Ravi Kumar Arimilli

发明人： Jerry Don Lewis ,  John Steven Dodson ,  Ravi Kumar Arimilli

IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F13/14

CPC分类号： G06F13/4213

摘要： A system and method for transferring bus operations in a processing system which includes at least one processor, the method and system include issuing a plurality of ordered bus operations by the at least one processor, wherein the plurality of bus operations include a first bus operation and a second bus operation, wherein the second bus operation is issued next after the first bus operation is issued. It also determines if a first response for the first bus operation has been received by the at least one processor prior to issuing the second bus operation, wherein the first response indicates that the first bus operation can be transferred. If the first response for the first bus operation is received by the at least one processor prior to issuing the second bus operation, a signal is provided along with the second bus operation, wherein the signal indicates that the processor will not issue a second response for the second bus operation, wherein the second response indicates that the second bus operation should be reissued.

摘要翻译： 一种用于在包括至少一个处理器的处理系统中传送总线操作的系统和方法，所述方法和系统包括由所述至少一个处理器发出多个有序总线操作，其中所述多个总线操作包括第一总线操作和 第二总线操作，其中在发出第一总线操作之后接下来发出第二总线操作。 它还确定在发出第二总线操作之前是否由至少一个处理器接收到第一总线操作的第一响应，其中第一响应指示可以传送第一总线操作。 如果在发出第二总线操作之前由至少一个处理器接收到第一总线操作的第一响应，则与第二总线操作一起提供信号，其中该信号指示处理器将不会发出第二响应 所述第二总线操作，其中所述第二响应指示应该重新发出所述第二总线操作。

公开(公告)号：US6128707A

公开(公告)日：2000-10-03

申请号：US176721

申请日：1998-10-21

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0879

摘要： System and method for selectively adapting the burst mode writeback from cache to main memory consistent with the extent of a cache line actually modified by the processor and at the granularity of the bus connecting the cache to main memory. A cache controller speculatively reads a cache line with each address issued by this processor. When the address is related to a read cycle of the processor, the data is forwarded to the processor. When the address is related to a write cycle of the processor, the data read from the cache is compared to the write data from the processor to detect changes at a granularity consist with the size of the system data bus. The cache line stored in the cache upon such writing is marked at the granularity of the system data bus with tag bits to indicate which portions have been modified. Upon deallocation, the tag bits stored in the cache directory identify those portions of the cache lines requiring transmission back to main memory as an aspect of the burst writeback operation.

摘要翻译： 系统和方法用于根据由处理器实际修改的高速缓存线的范围，以及将高速缓存连接到主存储器的总线的粒度，选择性地将缓存模式回写从高速缓存重新调整到主存储器。 高速缓存控制器推测性地读取由该处理器发出的每个地址的高速缓存行。 当地址与处理器的读取周期相关时，数据被转发到处理器。 当地址与处理器的写入周期相关时，将从高速缓存读取的数据与来自处理器的写入数据进行比较，以以系统数据总线的大小包含的粒度来检测变化。 在写入时存储在高速缓存中的高速缓存行以带有标记位的系统数据总线的粒度标记，以指示哪些部分已被修改。 在解除分配时，存储在高速缓存目录中的标签位将突发回写操作的一个方面标识出需要传输回主存储器的那些部分。

公开(公告)号：US6101582A

公开(公告)日：2000-08-08

申请号：US24639

申请日：1998-02-17

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0833

摘要： Depending on a processor or instruction mode, a data cache block store (dcbst) or equivalent instruction is treated differently. A coherency maintenance mode for the instruction, in which the instruction is utilized to maintain coherency between bifurcated data and instruction caches, may be entered by setting bits in a processor register or by setting hint bits within the instruction. In the coherency maintenance mode, the instruction both pushes modified data to system memory and invalidates the cache entry in instruction caches. Subsequent instruction cache block invalidate (icbi) or equivalent instructions targeting the same cache location are no-oped when issued by a processor following a data cache block store or equivalent instruction executed in coherency maintenance mode. Execution of the data cache clock store instruction in coherency maintenance mode results in a novel system bus operation being initiated on the system bus. The bus operation directs other devices having bifurcated data and instruction caches to clean the specified cache entry in their data cache to at least the point of instruction/data cache coherency and invalidate the specified cache entry in their instruction cache. When repeatedly employed in sequence to write one or more pages of data to system memory, the mechanism for maintaining coherency saves processor cycles and reduces both address and data bus traffic.

摘要翻译： 根据处理器或指令模式，数据高速缓存块存储（dcbst）或等效指令的处理方式不同。 可以通过设置处理器寄存器中的位或通过在指令内设置提示位来输入用于指令用于维持分支数据和指令高速缓存之间的一致性的指令的一致性维护模式。 在相干维护模式下，指令将修改的数据推送到系统存储器，并使指令高速缓存中的高速缓存条目无效。 随后指令高速缓存块无效（icbi）或针对同一高速缓存位置的等效指令在由数据高速缓存块存储器执行的处理器发出或在相干性维护模式下执行的等效指令时不会执行。 在一致性维护模式下执行数据高速缓存时钟存储指令导致在系统总线上启动新颖的系统总线操作。 总线操作指示具有分叉数据和指令高速缓存的其他设备将其数据高速缓存中的指定高速缓存条目清理为至少指令/数据高速缓存一致性点，并使其指令高速缓存中指定的高速缓存条目无效。 当重复按顺序将一个或多个数据页写入系统存储器时，用于维持一致性的机制节省了处理器周期，并减少了地址和数据总线流量。

公开(公告)号：US5937172A

公开(公告)日：1999-08-10

申请号：US839445

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00

CPC分类号： G06F12/0897 ,  G06F12/0893 ,  G06F13/1694

摘要： Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.

公开(公告)号：US5924121A

公开(公告)日：1999-07-13

申请号：US771995

申请日：1996-12-23

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0879

摘要： System and method for selectively adapting the burst mode writeback from cache to main memory consistent with the extent of a cache line actually modified by the processor and at the granularity of the bus connecting the cache to main memory. A cache controller speculatively reads a cache line with each address issued by this processor. When the address is related to a read cycle of the processor, the data is forwarded to the processor. When the address is related to a write cycle of the processor, the data read from the cache is compared to the write data from the processor to detect changes at a granularity consist with the size of the system data bus. The cache line stored in the cache upon such writing is marked at the granularity of the system data bus with tag bits to indicate which portions have been modified. Upon deallocation, the tag bits stored in the cache directory identify those portions of the cache lines requiring transmission back to main memory as an aspect of the burst writeback operation.

公开(公告)号：US5909698A

公开(公告)日：1999-06-01

申请号：US818845

申请日：1997-03-17

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0804 ,  G06F12/0808

摘要： In a processor employing separate instruction and data caches in at least one cache hierarchy level, a cache control instruction forces modified data within the separate data cache to a lower cache hierarchy level. An existing cache access attribute is employed to distinguish between occasions when the data must be written all the way to main memory and occasions when the data need only be written to a cache hierarchy level from which fetches are made to the separate instruction cache. Thus, the separate instruction and data caches may be made coherent without writing all the way to main memory, but the ability to write modified data to main memory whenever necessary is preserved. Utilization of the existing attribute avoids increasing processor complexity and/or resources.

摘要翻译： 在处理器中，在至少一个高速缓存层级中使用单独的指令和数据高速缓存，高速缓存控制指令强制单独的数据高速缓存内的修改的数据到较低的高速缓存层级。 采用现有的高速缓存访​​问属性来区分当数据必须一直写入主存储器的情况，并且当数据只需要写入到从其提取到高速缓存层级的高速缓存层级时。 因此，分离的指令和数据高速缓存可以一致地进行，而不必一直写入主存储器，而是保存在必要时将修改的数据写入主存储器的能力。 现有属性的利用避免了增加的处理器复杂性和/或资源。

公开(公告)号：US5895495A

公开(公告)日：1999-04-20

申请号：US815647

申请日：1997-03-13

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

IPC分类号： G06F9/52 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177 ,  G06F13/16

CPC分类号： G06F12/0811

摘要： A method of handling load-and-reserve instructions in a multi-processor computer system wherein the processing units have multi-level caches. Symmetric multi-processor (SMP) computers use cache coherency to ensure the same values for a given memory address are provided to all processors in the system. Load-and-reserve instructions used, for example, in quick read-and-write operations, can become unnecessarily complicated. The present invention provides a method of accessing values in the computer's memory by loading the value from the memory device into all of said caches, and sending a reserve bus operation from a higher-level cache to the next lower-level cache only when the value is to be cast out of the higher cache, and thereafter casting out the value from the higher cache after sending the reserve bus operation. This procedure is preferably used for all caches in a multi-level cache architecture, i.e., when the value is to be cast out of any given cache, a reserve bus operation is sent from the given cache to the next lower-level cache (i.e., the adjacent cache which lies closer to the bus), but the reserve bus operation is not sent to all lower caches. Any attempt by any other processing unit in the computer system to write to an address of the memory device which is associated with the value will then be forwarded to all higher-level caches. The marking of the block as reserved is removed in response to any such attempt to write to the address.

摘要翻译： 一种在多处理器计算机系统中处理加载和备用指令的方法，其中所述处理单元具有多级高速缓存。 对称多处理器（SMP）计算机使用高速缓存一致性来确保给定内存地址的相同值提供给系统中的所有处理器。 例如，在快速读写操作中使用的加载和备份指令可能会变得不必要的复杂。 本发明提供了一种通过将来自存储器设备的值加载到所有高速缓存中来访问计算机存储器中的值的方法，并且只有当值从高级高速缓存发送到下级高级缓存时， 将被抛出较高的缓存，然后在发送备用总线操作之后从较高的缓存中输出该值。 该过程优选地用于多级高速缓存架构中的所有高速缓存，即，当该值将从任何给定的高速缓存中抛出时，预留总线操作从给定的高速缓存发送到下一级的高级缓存（即 ，靠近总线的相邻缓存），但是备用总线操作不发送到所有较低的高速缓存。 计算机系统中的任何其他处理单元尝试写入与该值相关联的存储器件的地址然后将被转发到所有更高级别的高速缓存。 响应于写入地址的任何此类尝试，删除块作为保留的标记。

公开(公告)号：US06701416B1

公开(公告)日：2004-03-02

申请号：US09024620

申请日：1998-02-17

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F1200

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.

摘要翻译： 高速缓存一致性协议使用“标记”一致性状态跟踪将修改后的值写回系统内存的责任，允许干预该值而不会立即将其写回系统内存，从而增加内存带宽。 当分配给最近加载修改值的高速缓存行时，Tagged状态可以跨缓存迁移（水平）。 与Tagged状态有关的历史状态可能会被进一步使用。 本发明还可以应用于具有群集处理单元的多处理器计算机系统，使得标签状态可以应用于支持单独处理单元群集的每组高速缓存中的一个高速缓存行。 优先级被分配给不同的缓存状态，包括标签状态，用于响应访问对应的存储器块的请求。 任何标记的干预响应只能转发到可能受到干预响应影响的所选高速缓存，使用交叉条。 标签协议可以与现有的和新的高速缓存一致性协议相结合。 本发明进一步考虑使用标签状态对高速缓存操作的独立优化。

公开(公告)号：US06587926B2

公开(公告)日：2003-07-01

申请号：US09903729

申请日：2001-07-12

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F1200

CPC分类号： G06F3/0601 ,  G06F2003/0697

摘要： A method and system for managing a data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device to multiple data storage devices within the hierarchical data storage system. The data access request includes a source path tag and a target address. At least one device identification tag is added to the source path tag, wherein the at least one device identification tag uniquely identifies a data storage device within each level of the hierarchical data storage system traversed by the data access request such that the data access transaction can be processed in accordance with source path information that is incrementally encoded within the data access request as the data access request traverses the hierarchical data storage system.

摘要翻译： 一种用于管理层级数据存储系统内的数据访问事务的方法和系统。 根据本发明的方法，将数据访问请求从源设备传送到分级数据存储系统内的多个数据存储设备。 数据访问请求包括源路径标签和目标地址。 至少一个设备标识标签被添加到源路径标签，其中至少一个设备标识标签唯一地标识由数据访问请求遍历的分级数据存储系统的每个级别内的数据存储设备，使得数据访问事务可以 根据在数据访问请求遍历分层数据存储系统时在数据访问请求内逐步编码的源路径信息进行处理。

公开(公告)号：US06587925B2

公开(公告)日：2003-07-01

申请号：US09903728

申请日：2001-07-12

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F1200

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A method and system for processing a split data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device onto an address bus that is shared by a plurality of data storage devices within the hierarchical data storage system, wherein the data access request includes a target address and a source path tag. The source path tag includes at least one device identification tag that uniquely identifies at least one data storage device within each level of the hierarchical data storage system traversed by the data access request. In response to a data access request hit at a given data storage device, a data access response is delivered onto a data bus, wherein the data access response includes the source path tag and the target address.

摘要翻译： 一种用于处理分层数据存储系统内的分割数据访问事务的方法和系统。 根据本发明的方法，将数据访问请求从源设备传送到由层级数据存储系统内的多个数据存储设备共享的地址总线上，其中数据访问请求包括目标地址 和源路径标签。 源路径标签包括至少一个设备标识标签，其唯一地标识由数据访问请求遍历的分级数据存储系统的每个级别内的至少一个数据存储设备。 响应于在给定数据存储设备处的数据访问请求命中，将数据访问响应传递到数据总线上，其中数据访问响应包括源路径标签和目标地址。