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229 条记录 (耗时 0.04 秒)

    Preamplification circuit
    81.
    发明授权
    Preamplification circuit 失效

    公开(公告)号：US06404282B2

    公开(公告)日：2002-06-11

    申请号：US09852738

    申请日：2001-05-11

    申请人： Tsuneo Kikuchi ,  Yuichi Sato

    发明人： Tsuneo Kikuchi ,  Yuichi Sato

    IPC分类号： H03F136

    CPC分类号： H03K5/02 ,  H03G1/0088

    摘要： According to a level of an input signal, first switching means performs control in such a way that only a first feedback resistor or the first and second feedback resistors become feedback resistors connected to amplifying means, and thereby allows the amplifying means to keep linearity without saturating even when the level of the input signal changes. Furthermore, when the input signal has a higher level than a predetermined threshold, a phase compensation capacitor is charged under the control of second switching means for phase compensation of the amplifying means. However, even when the input signal has a lower level than the predetermined threshold, the phase compensation capacitor is charged at predetermined timing under the control of third switching means, preventing a high current from being pulled into the amplifying means when the input signal changes from a lower level than the predetermined threshold to a higher level than the predetermined threshold, thereby reducing noise applied to an output signal.

    MOS logic circuit and semiconductor apparatus including the same
    82.
    发明授权
    MOS logic circuit and semiconductor apparatus including the same 失效
    MOS逻辑电路和包括其的半导体装置

    公开(公告)号：US06320423B1

    公开(公告)日：2001-11-20

    申请号：US09597240

    申请日：2000-06-20

    申请人： Yuichi Sato

    发明人： Yuichi Sato

    IPC分类号： H03K19094

    CPC分类号： H03K19/1737

    摘要： A MOS logic circuit includes: a pass-transistor logic circuit, including at least one first MOS transistor, for performing a predetermined logic operation to provide an output; and an amplifying circuit, including at least one second MOS transistor, for enhancing a driving capability of the output of the pass-transistor logic circuit. Each of the first MOS transistor and the second MOS transistor is a DTMOS transistor having a gate connected to an associated well in which a channel thereof is formed.

    摘要翻译： MOS逻辑电路包括：传输晶体管逻辑电路，包括至少一个第一MOS晶体管，用于执行预定的逻辑运算以提供输出; 以及包括至少一个第二MOS晶体管的放大电路，用于增强传输晶体管逻辑电路的输出的驱动能力。 第一MOS晶体管和第二MOS晶体管中的每一个是具有连接到其中形成沟道的关联阱的栅极的DTMOS晶体管。

    Product-sum calculation circuit constructed of small-size ROM
    84.
    发明授权
    Product-sum calculation circuit constructed of small-size ROM 失效
    产品总和计算电路由小尺寸ROM构成

    公开(公告)号：US6101522A

    公开(公告)日：2000-08-08

    申请号：US86486

    申请日：1998-05-29

    申请人： Yuichi Sato

    发明人： Yuichi Sato

    IPC分类号： G06F7/52 ,  G06F7/523 ,  G06F7/53 ,  G06F17/10 ,  G06F7/00

    CPC分类号： G06F7/523 ,  G06F7/49936

    摘要： There is provided is a product-sum calculation circuit which can be constructed of a ROM having a small capacity. In this product-sum calculation circuit, when multiplier selection signals A0 through A2 select X as a multiplier, a second selector circuit 103 selects a product Ck.times.X obtained by multiplying a multiplicand Ck by the multiplier X and outputs the same to an output control circuit 104. In this case, the output control circuit 104 outputs the product Ck.times.X without shifting the same. When the multiplier selection signals A0 through A2 select (2.sup.n)X as the multiplier, the second selector circuit 103 selects the product Ck.times.X obtained by multiplying the multiplicand Ck by the multiplier X and outputs the same to the output control circuit 104 similar to the case where the multiplier X is selected. In this case, the output control circuit 104 outputs (2.sup.n)-fold value of (Ck.times.X) by shifting leftward the product Ck.times.X by n bits. Therefore, merely by storing (Ck.times.X) in a data storage circuit 102, a (2.sup.n)-fold output of (Ck.times.X) can be obtained.

    摘要翻译： 提供了可以由具有小容量的ROM构成的乘积和计算电路。 在该乘积和计算电路中，当乘法器选择信号A0〜A2选择X作为乘法器时，第二选择电路103选择通过将乘法器Ck乘以乘法器X而获得的乘积CkxX，并将其输出到输出控制电路104 在这种情况下，输出控制电路104输出产品CkxX而不使其移位。 当乘法器选择信号A0至A2选择（2n）X作为乘法器时，第二选择器电路103选择通过将乘法器Ck乘以乘法器X而获得的乘积CkxX，并将其输出到输出控制电路104，类似于 选择乘数X。 在这种情况下，输出控制电路104通过向左移动乘积CkxX n比特来输出（CkxX）的（2n）倍值。 因此，仅通过将（CkxX）存储在数据存储电路102中，可以获得（CkxX）的（2n）倍的输出。

    Supplying method for molten alloy for producing amorphous alloy thin strip
    85.
    发明授权
    Supplying method for molten alloy for producing amorphous alloy thin strip 有权
    用于生产非晶合金薄带的熔融合金的供应方法

    公开(公告)号：US5965052A

    公开(公告)日：1999-10-12

    申请号：US178318

    申请日：1998-10-23

    申请人： Yuichi Sato ,  Shigekatsu Ozaki ,  Hideya Kuratani

    发明人： Yuichi Sato ,  Shigekatsu Ozaki ,  Hideya Kuratani

    IPC分类号： B22D11/06 ,  B22D37/00 ,  B22D41/18 ,  B22D41/50

    CPC分类号： B22D37/00 ,  B22D11/064 ,  B22D41/18 ,  B22D41/50

    摘要： A method for supplying molten metal alloy for producing thin amorphous metal wire or thin amorphous metal strip by liquid quenching and solidification on a moving cooling substrate controls the flow of molten metal from a ladle into a tundish. The ladle has a long nozzle with an interior passage for providing flow of molten metal alloy into the tundish. The ladle stopper has a distal end region received by the interior passage of the long nozzle. Control of the overlap between the distal end region of the ladle stopper received in the long nozzle during molten alloy flow and control of the sectional flow area provided in the long nozzle interior passage controls the flow quantity of molten alloy from the ladle into the tundish.

    摘要翻译： 用于通过液体淬火和固化在移动的冷却基板上提供用于制造薄的非晶金属线或薄的无定形金属带的熔融金属合金的方法控制熔融金属从钢包到中间包的流动。 钢包具有长的喷嘴，其具有用于将熔融金属合金流入中间包的内部通道。 钢包塞具有由长喷嘴的内部通道容纳的远端区域。 控制在熔融合金流动期间容纳在长喷嘴中的浇包止挡件的远端区域与设置在长喷嘴内部通道中的截面流动面积的控制之间的重叠控制熔融合金从钢包进入中间包的流量。

    Fe-system amorphous metal alloy strip having enhanced AC magnetic properties and method for making the same
    86.
    发明授权
    Fe-system amorphous metal alloy strip having enhanced AC magnetic properties and method for making the same 失效
    具有增强的交流磁性的铁系非晶金属合金带及其制造方法

    公开(公告)号：US5958153A

    公开(公告)日：1999-09-28

    申请号：US632374

    申请日：1996-04-10

    申请人： Hiroaki Sakamoto ,  Yuichi Sato ,  Toshio Yamada

    发明人： Hiroaki Sakamoto ,  Yuichi Sato ,  Toshio Yamada

    IPC分类号： H01F1/153 ,  H01F27/24

    CPC分类号： H01F1/15308 ,  H01F27/24

    摘要： An amorphous metal alloy strip having enhanced magnetic properties consisting essentially of a composition mainly composed of Fe, Si, B, C and P having the formula (Fe.sub.a Si.sub.b B.sub.c C.sub.d).sub.100-x P.sub.x, wherein "a", "b", "c" and "d" are atomic percentages ranging from 70 to 86, 1 to 19, 7 to 20 and 0.02 to 4, respectively, with the proviso that the sum of "a", "b", "c" and "d" is equal to 100, and "x" is a weight percentage ranging from 0.003 to 0.1, said alloy strip having a thickness of 40 to 90 .mu.m and a width of not less than 20 mm. This amorphous metal alloy strip can be produced by a sinle-roll or twin-roll process under a specific cooling condition.

    摘要翻译： 具有增强的磁特性的非晶金属合金带主要由主要由Fe，Si，B，C和P组成的组成，具有式（FeaSibBcCd）100-x Px，其中“a”，“b”，“c”和 “d”分别为70至86,1至19,7至20和0.02至4的原子百分比，条件是“a”，“b”，“c”和“d”之和相等 至100，“x”为0.003〜0.1的重量百分比，所述合金带的厚度为40〜90μm，宽度为20mm以上。 这种无定形金属合金带可以在特定冷却条件下通过正辊或双辊方法制造。

    Control circuit for data transfer between a main memory and a register file
    88.
    发明授权
    Control circuit for data transfer between a main memory and a register file 失效
    用于主存储器和寄存器文件之间的数据传输的控制电路

    公开(公告)号：US5483643A

    公开(公告)日：1996-01-09

    申请号：US39788

    申请日：1993-03-30

    申请人： Yuichi Sato

    发明人： Yuichi Sato

    IPC分类号： G06F9/34 ,  G06F9/312 ,  G06F12/02 ,  G06F13/00

    CPC分类号： G06F9/30043

    摘要： A control circuit for data transfer between a main memory and a register file. Firstly, the control circuit acquires, via a selector, a save area mask (SAM) data from external circuitry. A register file address generator produces a register file address using the SAM data which has been chosen by the selector. The register file address determines a location of a register in the register file. A SAM data renewal circuit is provided to renew the SAM data selected by the selector. The SAM data which has been renewed will be used for addressing another register in the register file. The renewal circuit supplies the selector with the SAM data which has been renewed. A controller is arranged to receive the SAM data chosen by the selector and generates a control signal according thereto. The control signal is applied to the selector and controls same such as to select the SAM data from the external circuit or the SAM data applied from the SAM data renewal circuit.

    摘要翻译： 用于在主存储器和寄存器文件之间进行数据传输的控制电路。 首先，控制电路经由选择器获取来自外部电路的保存区掩码（SAM）数据。 寄存器文件地址生成器使用由选择器选择的SAM数据产生寄存器文件地址。 寄存器文件地址确定寄存器文件中寄存器的位置。 提供SAM数据更新电路以更新由选择器选择的SAM数据。 已更新的SAM数据将用于寻址寄存器文件中的另一个寄存器。 更新电路为选择器提供已更新的SAM数据。 控制器被布置为接收由选择器选择的SAM数据，并根据其产生控制信号。 控制信号被施加到选择器并进行控制，以从外部电路选择SAM数据或从SAM数据更新电路应用的SAM数据。

    Image data reading apparatus
    90.
    发明授权
    Image data reading apparatus 失效
    图像数据读取装置

    公开(公告)号：US4933983A

    公开(公告)日：1990-06-12

    申请号：US13731

    申请日：1987-02-11

    申请人： Akira Hiramatsu ,  Yuichi Sato ,  Tokuichi Tsunekawa ,  Shigeki Yamada ,  Takeshi Kobayashi ,  Makoto Katsuma

    发明人： Akira Hiramatsu ,  Yuichi Sato ,  Tokuichi Tsunekawa ,  Shigeki Yamada ,  Takeshi Kobayashi ,  Makoto Katsuma

    IPC分类号： H04N1/401 ,  G06K9/00

    CPC分类号： H04N1/401

    摘要： An image data reading apparatus includes a photoelectric conversion device for converting image data on an original into electric signals, a light source for illuminating the original, a detector for detecting the shading correction values for the light source and the photoelectric conversion device, and an image processor for effecting shading correction on the video data output from the photoelectric conversion device with the shading correction value detected by the correction value detector.

    摘要翻译： 图像数据读取装置包括用于将原件上的图像数据转换为电信号的光电转换装置，用于照亮原件的光源，用于检测光源和光电转换装置的阴影校正值的检测器，以及图像 处理器，用于利用由校正值检测器检测到的阴影校正值对从光电转换装置输出的视频数据进行阴影校正。